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Placement for Field Effect Transistor Design

IP.com Disclosure Number: IPCOM000080508D
Original Publication Date: 1973-Dec-01
Included in the Prior Art Database: 2005-Feb-27
Document File: 3 page(s) / 25K

Publishing Venue

IBM

Related People

Hanan, M: AUTHOR [+2]

Abstract

A multitude of considerations must be taken into account when placing circuits in a field-effect transistor (FET) environment. The problem is entirely different from the case of bipolar transistors, where the time of flight is of importance [1]. The delay T of a stage is assumed to include the output net 0 of the stage, as shown in the figure. All device capacitances are lumped into C(D) while C(W) represents the capacitance of the wiring net 0. Then, the delay T is approximately proportional to C(N)=C(W)+C(D). Thus, reducing C(W) or C(D) separately may not lead to a large reduction of delay where needed, since for a good FET design C(W)= C(D). Thus, an upper bound of a factor 2 can be gained if either C(W) or C(D) is changed separately.

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Placement for Field Effect Transistor Design

A multitude of considerations must be taken into account when placing circuits in a field-effect transistor (FET) environment.

The problem is entirely different from the case of bipolar transistors, where the time of flight is of importance [1]. The delay T of a stage is assumed to include the output net 0 of the stage, as shown in the figure. All device capacitances are lumped into C(D) while C(W) represents the capacitance of the wiring net 0. Then, the delay T is approximately proportional to C(N)=C(W)+C(D). Thus, reducing C(W) or C(D) separately may not lead to a large reduction of delay where needed, since for a good FET design C(W)= C(D). Thus, an upper bound of a factor 2 can be gained if either C(W) or C(D) is changed separately.

The mechanisms for adju-sting C(W) are the FET gate width of the circuits C1-C4, while a new placement of the circuits C1-C4 will result in a change of C(W). It is proposed here, that the adjustment of C(W) and C(D) be used simultaneously to obtain a more optimal chip design. A first consideration is the requirement that the system timing is met, i.e., that all signals arrive at the appropriate time.

Secondly, the power dissipation of the chip is reduced.

Another important consideration is the iact that a system without capacitance- dependent circuit placement and wiring must necessarily be designed in a suboptimal way, since the inequality C(D)>>C(W) must hold. Mainly, the ratio of the average net distance d(N) (total length of wire/net) to longest net distance d(N max.) is 1/5 to 1/10. Thus, if T " C(N) = C(W) + C(D), the max. delay T(max.) due to C(W max.)= 10C(W), T(max.) = K(C(D) + 10C(D)) = 5.5T, where T is the average delay. Hence, the uncertainty in d(N) is responsible for a large variation in T. The large variation in T may be tolerable for noncritical nets. However, for critical nets, the wiring must be controlled. This is accomplished by the algorithm proposed in the next section. Algorithm. Let d(b) = avg. branch distance f = avg. fan-out then d(N) = f d(d) = avg. net distance. Using d(N), we find C(W) and compute a delay for each circuit. By using a timing analysis program, the required delay can be computed for each net. If the timing is not met for the net k, compute d(N(k)) = f(k) d(min.), where f(k) is the fan-out for net k and d(min) is the minimum spacing between circuits.

If d(N(k)) < d(N), that is if the theoretical minimum distance of net k is less than the assumed average distance, then t...