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Interleaved Memory Array

IP.com Disclosure Number: IPCOM000080510D
Original Publication Date: 1973-Dec-01
Included in the Prior Art Database: 2005-Feb-27
Document File: 2 page(s) / 32K

Publishing Venue

IBM

Related People

Hoffman, WK: AUTHOR

Abstract

Memory cell densities in an array are improved by nearly two-to-one by eliminating sense latch and regeneration circuits pitch restrictions, when the array employs cells each utilizing very small surface areas on a semiconductor medium. The improvement is obtained by interleaving the bit/sense lines, as illustrated in the drawing.

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Interleaved Memory Array

Memory cell densities in an array are improved by nearly two-to-one by eliminating sense latch and regeneration circuits pitch restrictions, when the array employs cells each utilizing very small surface areas on a semiconductor medium. The improvement is obtained by interleaving the bit/sense lines, as illustrated in the drawing.

When small cells 10, such as one-device cells, attached to bit/ sense lines 12 require a pitch of only about one-half of the pitch of the sense latch and regeneration circuits 14, the lines 12 coupled to opposite ends of circuits 14 are interleaved, so that two lines 12 are provided within the pitch of one of the sense latch and regeneration circuits 14. Word drive circuits 16, connected to word lines, not shown, which are disposed orthogonal to the bit/sense lines 12 and also coupled to cells 10, are located outside of the cell area and do not affect the high density provided by the interleaved lines 12.

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