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Browse Prior Art Database

Simplified Control of Memory Arrays

IP.com Disclosure Number: IPCOM000080538D
Original Publication Date: 1974-Jan-01
Included in the Prior Art Database: 2005-Feb-27
Document File: 2 page(s) / 32K

Publishing Venue

IBM

Related People

Christensen, NT: AUTHOR [+4]

Abstract

This circuit provides an access to a memory array where data is stored in an array and read out some fixed time interval after it is stored.

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Simplified Control of Memory Arrays

This circuit provides an access to a memory array where data is stored in an array and read out some fixed time interval after it is stored.

The circuit is driven by three external signals. A SELECT signal 10 which causes data to be written into a location in the array, an ADVANCE signal 12 which causes data to be read out of a location in the array, and a STOP signal 14 which inhibits further read and write operation.

In the absence of a STOP signal 14, a SELECT signal 10 causes an entry to be loaded into the array 16. The array address location X into which the entry is loaded is determined by the output of the incrementer triggers 18, which also triggers the incrementer 2O. The incrementer then advances the incrementer latches 22 to the next address in the sequence. Therefore, when the ADVANCE 12 signal for that entry is received, `A' cycles after the SELECT signal 10 for the entry, the contents of the incrementer latches 22 are at address X + A. This address is gated simultaneously into the incrementer and retain triggers 18 and
24. The contents of the retain triggers 24 are decremented by the subtractor 26 by the amount A, and this decremented value (X + A - A = X) is used to address the array 16 for reading. Thus, the contents read out for the ADVANCE are the same as were stored for its corresponding SELECT.

The STOP signal 14 indicates that some specified error condition exists with respect to the last ADVANCE, and cause...