Browse Prior Art Database

Digital Phase Lock Oscillator

IP.com Disclosure Number: IPCOM000080539D
Original Publication Date: 1974-Jan-01
Included in the Prior Art Database: 2005-Feb-27
Document File: 2 page(s) / 43K

Publishing Venue

IBM

Related People

Collins, CA: AUTHOR

Abstract

This phase-lock oscillator can be implemented entirely using logic blocks.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 100% of the total text.

Page 1 of 2

Digital Phase Lock Oscillator

This phase-lock oscillator can be implemented entirely using logic blocks.

The loop 10 comprises a local oscillator whose output 12 is compared with the output 14 of a master oscillator in an AND invert circuit 16. The output 18 of the circuit 16 controls the data stored in the shift register 20 at any given clock time, determined by output 22 of the clock pulse generator. When the outputs 12 and 14 are in synchronism a "1" is produced at the output 18 of the AND invert circuit 16, for storage in one of the stages of the shift register 20 that is at the input of the shift register at the time the clock pulse on line 22 comes up.

Each stage of the shift register 20 is fed to one of twenty AND invert circuits 22 so that if a 1 is stored in a stage, the particular AND invert circuit acts as a load on the oscillator. While if a "0" is stored in the stage coupled to the input of the AND invert circuit 22, the AND invert circuit does not load the oscillator. In this way, the data in the twenty-stage shift register 20 changes until the output 12 of the local oscillator is in synchronism with the output 14 of the master oscillator.

1

Page 2 of 2

2

[This page contains 4 pictures or other non-text objects]