Browse Prior Art Database

Refresh Generator

IP.com Disclosure Number: IPCOM000080556D
Original Publication Date: 1974-Jan-01
Included in the Prior Art Database: 2005-Feb-27
Document File: 2 page(s) / 59K

Publishing Venue

IBM

Related People

Paniccia, AE: AUTHOR

Abstract

For the application and testing of Metal-Alumina-Oxide Semiconductor Read-Mostly Memory (MAOS RMM) chips, a write and erase function is required to initialize and change information stored in memory. These functions require data to be entered and retained in a dynamic on-chip data shift register (SR). The time required to write and erase is greater than the retention time of the data SR, and it is therefore necessary to refresh the entered data. The refresh generator provides a refresh pulse of sufficient duration to restore the data entered, and at a period less than the retention time of the data shift register.

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Refresh Generator

For the application and testing of Metal-Alumina-Oxide Semiconductor Read-Mostly Memory (MAOS RMM) chips, a write and erase function is required to initialize and change information stored in memory. These functions require data to be entered and retained in a dynamic on-chip data shift register (SR). The time required to write and erase is greater than the retention time of the data SR, and it is therefore necessary to refresh the entered data. The refresh generator provides a refresh pulse of sufficient duration to restore the data entered, and at a period less than the retention time of the data shift register.

The refresh generator consists of three DECADE COUNTERS and associated control circuitry. COUNTER 1 divides the input frequency by ten. COUNTERS 2 and 3 provide alternate refresh pulses with the pulse width controlled by TRIGGER T1. The CLOCK CONTROL LATCH guarantees that a partial INPUT CLOCK pulse will not produce partial clock pulse BD1, which will effect refresh precision. When START/STOP REFRESH goes high, the INPUT CLOCK must first go low. The following high CLOCK INPUT will then be allowed to pulse COUNTER 1 (BD1).

TRIGGER T1 output QR clocks COUNTER 2 and QR clocks COUNTER 3. TRIGGER T1 changes states for each ten clock pulses BD1. COUNTER 2 output A2 will go high before COUNTER 3 output A3. TRIGGERS T2 and T3 are cleared while A2 and A3 outputs are low. When A2 goes high, TRIGGER T2 QA is high and when TRIGGER T1 QR goes high, the AND gate is satisfied and point R1 goes high making REFRESH OUTPUT high. Point R1 also resets COUNTER 3 p...