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Uniprocessor Buffer Invalidation Address Mechanism

IP.com Disclosure Number: IPCOM000080573D
Original Publication Date: 1974-Jan-01
Included in the Prior Art Database: 2005-Feb-27
Document File: 2 page(s) / 44K

Publishing Venue

IBM

Related People

Jones, JD: AUTHOR [+2]

Abstract

This mechanism permits the processing of channel storage requests. When the channels are making a storage request to an address which is valid in the high-speed buffer, that particular entry gets invalidated or updated. To update or invalidate the high-speed buffer it takes two cycles, one to see if the data is in the buffer and another to invalidate the entry. Since the channels are capable of making storage requests every cycle, this means that sooner or later there will be a conflict in accessing the high-speed buffer. An example of such a conflict is shown in Fig. 1.

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Uniprocessor Buffer Invalidation Address Mechanism

This mechanism permits the processing of channel storage requests. When the channels are making a storage request to an address which is valid in the high-speed buffer, that particular entry gets invalidated or updated. To update or invalidate the high-speed buffer it takes two cycles, one to see if the data is in the buffer and another to invalidate the entry. Since the channels are capable of making storage requests every cycle, this means that sooner or later there will be a conflict in accessing the high-speed buffer. An example of such a conflict is shown in Fig. 1.

To overcome this problem, buffer invalidation address stacks 10 and 12, Fig. 2, are used to serve as an interface between the CPU's 14 and 16 and the high- speed buffers 18 and 20. When one CPU 14 makes a store request not only will its own buffer 18 be updated or invalidated, but also the other CPU's buffer 20 will be invalidated by placing the requests in both invalidation stacks 10 and 12.

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