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Address Validity Checking During a Program Execution Test

IP.com Disclosure Number: IPCOM000080587D
Original Publication Date: 1974-Jan-01
Included in the Prior Art Database: 2005-Feb-27
Document File: 2 page(s) / 13K

Publishing Venue

IBM

Related People

Bouillot, M: AUTHOR [+2]

Abstract

In view of detecting addressing errors (relocation errors, zone errors, etc.), check bits are added to each word for identifying the nature of the information contained in the word (data or address) and, in the case of extended address, the partition. During the preparation and the execution of the instructions, the CPU processes the check bits for detecting errors. This technique is applicable either directly by additional register positions and additional logic circuitry in the machine, or in a simulation way by introducing such registers and logic in the simulator able to exercise the program.

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Address Validity Checking During a Program Execution Test

In view of detecting addressing errors (relocation errors, zone errors, etc.), check bits are added to each word for identifying the nature of the information contained in the word (data or address) and, in the case of extended address, the partition. During the preparation and the execution of the instructions, the CPU processes the check bits for detecting errors. This technique is applicable either directly by additional register positions and additional logic circuitry in the machine, or in a simulation way by introducing such registers and logic in the simulator able to exercise the program.

A relocation error occurs if the calculation of the effective ad address requires: - adding together two relocatable values, - subtracting a relocatable data value from an absolute data value.

Moreover, in the case of expanded storage, the effective address can refer to an address in a different storage partition than the instruction location itself. In such a case, a change must happen during execution of the instruction.

The purpose of the method is to detect the cases in which the transformation of the basic instruction has not been done or has been done wrong. Errors can happen in particular when transformations must be done manually by the programmer in the case of indirect addressing or address indexing. The hereinafter described method allows detection of such errors.

According to this method, checking of both relocation validity and partition addressing validity will apply at program simulation time. With each word and each register of the simulated machine, are associated three bits: - one is a relocation bit, of value 1 if the data contained in the word is relocatable, 0 if the data is absolute. - two are partition addressing bits, of value 00, 01, 10, 11 according to the partition in which the data contained in

the word is relocatable and located.

The relocation bit R is posted by the Assembler, the partition bits P are posted by the...