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Low Capacitance Semiconductor Bit Line Structure

IP.com Disclosure Number: IPCOM000080606D
Original Publication Date: 1974-Jan-01
Included in the Prior Art Database: 2005-Feb-27
Document File: 1 page(s) / 11K

Publishing Venue

IBM

Related People

Garnache, RR: AUTHOR

Abstract

It has been found that low-capacitance bit line configurations in single-device memory cell structures can be accomplished, by completely selectively oxidizing the polycrystalline field-shield layer to the underlaying oxide-nitride composite insulating layer. This procedure necessitates a relatively long hot processing step, and requires a special provision for contact to diffusions on the bit line with consequent decrease in density.

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Low Capacitance Semiconductor Bit Line Structure

It has been found that low-capacitance bit line configurations in single-device memory cell structures can be accomplished, by completely selectively oxidizing the polycrystalline field-shield layer to the underlaying oxide-nitride composite insulating layer. This procedure necessitates a relatively long hot processing step, and requires a special provision for contact to diffusions on the bit line with consequent decrease in density.

The aforesaid disadvantage may be eliminated by thermally oxidizing the polycrystalline silicon partially, e.g., about halfway, to the oxide-nitride insulating area, followed by removing the silicon nitride previously deposited upon the polycrystalline silicon, thereby leaving a thin layer of polycrystalline silicon over the bit line. Followed by masking and removal of polycrystalline silicon from the gate area and subsequent thermal oxidation, will remove the remaining polycrystalline silicon over the bit line.

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