Dismiss
InnovationQ will be updated on Sunday, Oct. 22, from 10am ET - noon. You may experience brief service interruptions during that time.
Browse Prior Art Database

Semiconductor Solder Reflow Chip Substrate Joining

IP.com Disclosure Number: IPCOM000080649D
Original Publication Date: 1974-Jan-01
Included in the Prior Art Database: 2005-Feb-27
Document File: 2 page(s) / 29K

Publishing Venue

IBM

Related People

Chase, EN: AUTHOR [+2]

Abstract

In joining semiconductor device chips to conductive lands on conventional substrates by the reflow of solder balls or pads, which provide both the electrical connection to the conductive lands and mechanical support for the chip, thermal stress on these pad joints may cause processing problems. These problems may be eliminated by eliminating the first reflow step.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 100% of the total text.

Page 1 of 2

Semiconductor Solder Reflow Chip Substrate Joining

In joining semiconductor device chips to conductive lands on conventional substrates by the reflow of solder balls or pads, which provide both the electrical connection to the conductive lands and mechanical support for the chip, thermal stress on these pad joints may cause processing problems. These problems may be eliminated by eliminating the first reflow step.

Conventionally, a chip 1 is subjected to deposition of solder pads 2 of lead-tin composition or other suitable metal, as shown in Fig. 1. The chip is heated to an appropriate temperature and the solder pads 2 reflowed to a configuration shown in Fig. 2 at 2a. The chip is then superimposed on the substrate 3 with pads resting on land pattern 4, as shown in Fig. 3. Joining the chip 1 to the substrate 3, as illustrated in Fig. 4, is accomplished by a second and final heating to accomplish mechanical and electrical connection, where solder connections are illustrated by 2b in Fig. 4. This reflow technique is believed to reduce solder joining contact area at the chip, thus not providing optimum electrical and mechanical joining.

It has been found that the first heating and reflow from the configuration of Fig. 1 to Fig. 2 can be eliminated, and joining accomplished by one reflow direct from the Fig. 1 structure to the final joining in Figs. 5 and 6, leaving a connection as shown at 2c.

1

Page 2 of 2

2

[This page contains 2 pictures or other non-text objects]...