Browse Prior Art Database

Data Driver and Detector Circuit

IP.com Disclosure Number: IPCOM000080656D
Original Publication Date: 1974-Jan-01
Included in the Prior Art Database: 2005-Feb-27
Document File: 2 page(s) / 51K

Publishing Venue

IBM

Related People

Chin, W: AUTHOR

Abstract

This circuit utilizes complementary metal-oxide semiconductor (CMOS) devices, to provide an alterable impedance detector and driver to interface with a memory array. The circuit presents a high-input impedance to the memory when used as a data detector, and a low-output impedance when used as a data driver. The alterable impedance characteristic reduces the power dissipation when the circuit is used as a detector, and improves circuit performance when used as a driver.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 58% of the total text.

Page 1 of 2

Data Driver and Detector Circuit

This circuit utilizes complementary metal-oxide semiconductor (CMOS) devices, to provide an alterable impedance detector and driver to interface with a memory array. The circuit presents a high-input impedance to the memory when used as a data detector, and a low-output impedance when used as a data driver. The alterable impedance characteristic reduces the power dissipation when the circuit is used as a detector, and improves circuit performance when used as a driver.

Referring to the figure, for the transmit (write) operation receive line 33 is at ground; therefore, device P1 is off and N1 is turned on. In addition, transmit line 31 is at potential -VH, thereby turning device P4 on and N4 off. Data line 37 is either at logical 0 or logical 1. If it is in the former condition, P3 is turned off and N3 is turned on; thus node A is charged up to -VH through devices N1 and N3. Data is then ingated to the gated data register 2 when the read/write ingate clock pulse 2 on line 34 goes to -VH. The outputs of register 2, lines 35 and 36 remain at -VH and at ground, respectively, when line 34 returns to ground.

The negative potential at line 35 turns devices P12 and P9 on and turns devices N12 and N9 off. Node C is discharged to ground through P9 and insures that P10 is off. Device P11 is on and N11 is off, as transmit line 31 is at -VH. Thus Node D is discharged to ground through P11 and P12. This turns on device N10 to charge memory line...