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Forming Complementary Field Effect Devices and NPN Transistors

IP.com Disclosure Number: IPCOM000080664D
Original Publication Date: 1974-Jan-01
Included in the Prior Art Database: 2005-Feb-27
Document File: 3 page(s) / 82K

Publishing Venue

IBM

Related People

Antipov, I: AUTHOR

Abstract

In this process, blanket layers of polysilicon 10, SiO(2) 12, Si(3) N(4) 14, and SiO(2) 16 are deposited on a P-silicon wafer 8 by conventional deposition techniques. With a first mask that defines all future P-type areas, such as N channel devices, isolation regions for bipolar devices, and Schottky diodes, layer 10, 12, 14 and 16 are removed using conventional photolithographic and etching techniques, resulting in opening 18. The exposed surface of wafer 8 is then thermally oxidized forming thermal oxide layer 20, as shown in Fig. 1.

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Forming Complementary Field Effect Devices and NPN Transistors

In this process, blanket layers of polysilicon 10, SiO(2) 12, Si(3) N(4) 14, and SiO(2) 16 are deposited on a P-silicon wafer 8 by conventional deposition techniques. With a first mask that defines all future P-type areas, such as N channel devices, isolation regions for bipolar devices, and Schottky diodes, layer 10, 12, 14 and 16 are removed using conventional photolithographic and etching techniques, resulting in opening 18. The exposed surface of wafer 8 is then thermally oxidized forming thermal oxide layer 20, as shown in Fig. 1.

With a second mask that defines the P+ areas within the future P regions, as defined by the first mask, and N+ regions, an opening 22 is made in layer 20, and openings 23 and 24 in layer 16, as shown in Fig. 2. P+ region 25 is formed by conventional diffusion and the surface subsequently reoxidized. The openings 23 and 24 are then extended through layers 10, 12 and 14 by dip etching. N+ regions 26 and 27 are formed of an N+ impurity having a slow diffusivity type. The exposed surface of wafer 8 is then reoxidized forming SiO(2) layers 28 and 29, as shown in Fig. 3. The remaining portions of layers 12, 14 and 16 that form collars around the N regions are removed by dip etching.

Regions 30 are formed by diffusing an N-type impurity having a fast diffusivity into the resultant exposed openings through silicon layer 10, as shown in Fig. 4. The N+ regions 30 will eventually serve as collector contacts to bipolar devices or silicon contacts for Schottky diodes. They will also form heavily doped N+ regions around P channel integrated gate field-effect transistor (IGFET) devices and, therefore, reduce lateral PNP beta of these devices to negligible small numbers. The oxide is then removed from the surface of wafer 8 and then epitaxial layer 32 deposited on the surface, as shown in Fig. 5.

During the epitaxial deposition, the fast N+ impurities in regions 30 diffuse upwardly more rapidly than...