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Bipolar FET High Performance Circuit

IP.com Disclosure Number: IPCOM000080675D
Original Publication Date: 1974-Jan-01
Included in the Prior Art Database: 2005-Feb-27
Document File: 3 page(s) / 45K

Publishing Venue

IBM

Related People

Castrucci, PP: AUTHOR [+2]

Abstract

Integrating high-current, high-performance bipolar driver circuits with low-power, high-density complimentary metal-oxide semiconductor field-effect transistor (CMOS FET) logic circuits, represents an improved structure power/performance wise. Described is a monolithic circuit structure and process for combining these device technologies in a minimum number of sequences. The example given is an NPN bipolar device with low-collector impedance which drives a complementary FET logic array, in which the threshold voltage matching between N channel and P-channel devices is a maximum.

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Bipolar FET High Performance Circuit

Integrating high-current, high-performance bipolar driver circuits with low- power, high-density complimentary metal-oxide semiconductor field-effect transistor (CMOS FET) logic circuits, represents an improved structure power/performance wise. Described is a monolithic circuit structure and process for combining these device technologies in a minimum number of sequences. The example given is an NPN bipolar device with low-collector impedance which drives a complementary FET logic array, in which the threshold voltage matching between N channel and P-channel devices is a maximum.

This logic circuit configuration consists of the FET array positioned centrally on the chip, surrounded by the bipolar drive circuitry constituting the periphery. See Fig. 1.

This concept has equal validity for memory. In this case, support circuits, i.e., decoders, sense amplifiers as well as memory drives, are fabricated and integrated in a FET memory chip as to significantly reduce line delays prevalent, when these are designed in discrete circuits.

The following process summarizes key operations in the fabrication of this structure. The vertical structure is displayed in Fig. 2.

The basic process difficulty resolved by this design, is the fabrication f both N and PP-type regions required by the NPN driver or PNP drivers and FET circuit structures on the same wafer. The N-type region should have a maximum concentration to allow for minimum collector impedance, while yielding a minimum...