Browse Prior Art Database

Clocked and Binary Pulse Width Modulator Demodulator

IP.com Disclosure Number: IPCOM000080691D
Original Publication Date: 1974-Jan-01
Included in the Prior Art Database: 2005-Feb-27
Document File: 2 page(s) / 40K

Publishing Venue

IBM

Related People

Rosen, EW: AUTHOR [+2]

Abstract

Data sent to and received from terminal devices is often transmitted serially-by-bit over a coaxial cable. The data is pulse-width modulated with a short pulse designating a 0 bit, while a pulse of longer duration stipulates a 1 bit. Modulation and demodulation can be accomplished by use of a clock and shift registers instead of conventional precision single-shots.

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Clocked and Binary Pulse Width Modulator Demodulator

Data sent to and received from terminal devices is often transmitted serially- by-bit over a coaxial cable. The data is pulse-width modulated with a short pulse designating a 0 bit, while a pulse of longer duration stipulates a 1 bit. Modulation and demodulation can be accomplished by use of a clock and shift registers instead of conventional precision single-shots.

Referring to the figure, pulse-width modulated data appears on line Data In as an input to both demodulator 1 and serializer-deserializer (SerDes) 2. When the Receive line is activated, the reset is removed from demodulator 1 which begins to measure the length of the incoming pulse. Demodulator 1 is shifted by the clock until the leading edge of the clock pulse turns on position three. At this time position four is off. When the clock pulse falls, AND gate A3 is satisfied causing SerDes 2 to shift. If a 0 is received, Data In is still up and a 1 is shifted into SerDes 2. On the next pulse, position four is up, deactivating A3. This procedure is continued until the entire message is contained in SerDes 2, at which time it is gated out in parallel to external registers.

In the send mode, bits are inserted in parallel into SerDes 2 from external buffers. The Send line is activated, which conditions AND gate A4 and removes the reset from sequencer 5. The sequencer is a shift register with one circulating bit stepped at each clock time. The outputs of th...