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Voltage Regulator Sense Circuit

IP.com Disclosure Number: IPCOM000080715D
Original Publication Date: 1974-Feb-01
Included in the Prior Art Database: 2005-Feb-27
Document File: 2 page(s) / 35K

Publishing Venue

IBM

Related People

Kruggel, RH: AUTHOR

Abstract

The circuit detects small amounts of charge stored in an environment of large capacitive loading, such as is encountered in memory arrays of the type described in U.S. patent 3,387,286, entitled Field-Effect Transistor Memory, by using a voltage regulator as a low-impedance source for charging the bit/sense line and for sensing current flow from a selected cell.

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Voltage Regulator Sense Circuit

The circuit detects small amounts of charge stored in an environment of large capacitive loading, such as is encountered in memory arrays of the type described in U.S. patent 3,387,286, entitled Field-Effect Transistor Memory, by using a voltage regulator as a low-impedance source for charging the bit/sense line and for sensing current flow from a selected cell.

Field-effect transistors (FET's) T1, T2, T3 and T4 form a differential amplifier with T4 being an equivalent load resistor and T1 acting as a current source. FET T5 establishes a negative feedback from the drain to the gate of T3. Voltage V(1) has a value somewhat greater than the threshold voltage of T4 and voltage V(2) is greater than voltage V(R).

In operation, assuming that the bit/sense line is at zero or ground potential, with clock pulse phi 1 also at ground potential and clock pulse phi 2 at +V volts, T4 discharges the gate capacitance of T5 to ground and both T3 and T5 are turned off. When phi 1 goes positive, the gate of T5 also goes positive turning on T5 and charging the bit/ sense line. As the bit/sense line voltage approaches a value V(R), T3 begins to conduct and the voltage at the gate of T5 decreases. This action continues until T5 turns off and the following condition prevails: The bit/sense line voltage V(BS) is approximately equal to V(R), the gate voltage of T5 is equal to V(BS) plus the threshold voltage of T5, which condition can be reached in approximately 50 to 75 ns with N-channel devices, and capacitor C(L) is charged to approximately the voltage V(2).

Clock pulse 02...