Browse Prior Art Database

Sense Latch Circuit for Memory Cells

IP.com Disclosure Number: IPCOM000080720D
Original Publication Date: 1974-Feb-01
Included in the Prior Art Database: 2005-Feb-27
Document File: 3 page(s) / 39K

Publishing Venue

IBM

Related People

Furman, A: AUTHOR [+2]

Abstract

This sense latch circuit simplifies transfer of data into and out of memory cells, e.g., of the one-device type described in U.S. Patent 3,387,286, and eliminates or at least minimizes noise components, due to bit-line capacitance imbalances when coupling a pair of bit lines to opposite sides of the latch circuit, in order to sense very small data signals from the memory cells.

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Sense Latch Circuit for Memory Cells

This sense latch circuit simplifies transfer of data into and out of memory cells, e.g., of the one-device type described in U.S. Patent 3,387,286, and eliminates or at least minimizes noise components, due to bit-line capacitance imbalances when coupling a pair of bit lines to opposite sides of the latch circuit, in order to sense very small data signals from the memory cells.

In one cycle of operation, field-effect transistors (FET's) Tl and T2 are turned on by clock pulse 02 to charge nodes VA and VB to 3.5 volts, while clock pulse 01 is applying 3.5 volts to the sources of T3 and T4, interconnected as a latch, to maintain T3 and T4 in an off condition. Clock pulse 02 also turns on T5 and T6 to charge bit lines 10 and 12 to the 3.5 volts of clock pulse 04, precharging bit lines 10 and 12 as well as nodes VA and VB to 3.5 volts, thus eliminating any difference mode signal internal to the latch or on the bit lines.

To read a memory cell, e.g., cell 14 coupled to bit line 10, clock pulse phi 3 is applied to the gates of T8 and T9, to connect bit lines 10 and 12 to the latch T3, T4 at nodes VA and VB, respectively, and voltage Vw is applied from word line 16 to the gate of T7 to connect storage capacitor 18 of cell 14 to bit line 10. Depending upon the data, 1 or 0, represented as a high or low voltage, stored in storage capacitor 18, the voltage on bit line 10 will either increase or decrease from the previously charged 3.5 volt reference value. A difference mode signal VL is thereby impressed between nodes VA and VB, and then clock pulse phi 3 turns off to lock the difference signal VL internal to the latch on latch capacitances CL1 and CL2, which are small fractions of the bit line capacitances CBS1 and CBS2.

Now proceeding in parallel, are the operations of charging bit lines 10 and 12 and regenerating the signal VL in latch T3, T4. Clock pulse 01 drops to zero and the signal VL begins to increase in magnitude, due to the regenerative action of the latch or cross-coupled pair of transistors T3 and T4. Clock pulse 02 turns on T1 and T2 to complete the regeneration of signal VL, T1 and T2 being current limiting. During regenera...