Browse Prior Art Database

Refreshable Technique to Overcome Fatigue in Nonvolatile Memory for Random Access Memory Applications

IP.com Disclosure Number: IPCOM000080726D
Original Publication Date: 1974-Feb-01
Included in the Prior Art Database: 2005-Feb-27
Document File: 1 page(s) / 11K

Publishing Venue

IBM

Related People

Keshaven, BV: AUTHOR [+2]

Abstract

Nonvolatile memory devices fatigue under repeated read-write-erase cycles, which are in the order of 10/6/ or 10/7/ cycles. Such fatigue manifests itself on the operation of the nonvolatile memory by causing the threshold voltages representing a logic 0 or a logic 1 to shift to higher values, while narrowing the logic separation and decreasing the retention time of the information.

This text was extracted from a PDF file.
This is the abbreviated version, containing approximately 100% of the total text.

Page 1 of 1

Refreshable Technique to Overcome Fatigue in Nonvolatile Memory for Random Access Memory Applications

Nonvolatile memory devices fatigue under repeated read-write-erase cycles, which are in the order of 10/6/ or 10/7/ cycles. Such fatigue manifests itself on the operation of the nonvolatile memory by causing the threshold voltages representing a logic 0 or a logic 1 to shift to higher values, while narrowing the logic separation and decreasing the retention time of the information.

Such fatigue is attributed to the increase in fast-state density, created by the application of 10/7/ volts per centimeter or greater across the oxide during the write-erase cycles. Because of such fatigue, these nonvolatile memories may not be used for random-access memories which requires greater than 10 write- erase cycles.

However, if the nonvolatile memory cell device is erased, and is refreshed either by writing or erasing of it prior to the time before it loses its detectable threshold voltage due to fatigue, the nonvolatile device is returned back to its original threshold, thus resulting in a device effectively without fatigue. If it is assumed that a memory chip has approximately 128 cells common to the bit line, then the cell can be interrogated for approximately one quarter of a million cycles before refresh is required.

1