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Distributive Control for Large Scale Integration System Designs

IP.com Disclosure Number: IPCOM000080751D
Original Publication Date: 1974-Feb-01
Included in the Prior Art Database: 2005-Feb-27
Document File: 3 page(s) / 62K

Publishing Venue

IBM

Related People

Shimp, EM: AUTHOR [+2]

Abstract

Implementation of data processing systems using large-scale integrated (LSI) circuit technology, shows that as high as 60% of the chip part numbers are chips that are only used one time in the design. Most of these one-time usage parts consist of control logic which, because of its complexity and timing, makes it unique and prohibits usage of it in more than one place in the machine. During the design and debug of a system, the control logic is most susceptible to functional changes and logic errors, making it a leading candidate for Engineering Changes. Any chip change in LSI is next to impossible, resulting in the design of a new chip and a complete scrap of the old chip.

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Distributive Control for Large Scale Integration System Designs

Implementation of data processing systems using large-scale integrated (LSI) circuit technology, shows that as high as 60% of the chip part numbers are chips that are only used one time in the design. Most of these one-time usage parts consist of control logic which, because of its complexity and timing, makes it unique and prohibits usage of it in more than one place in the machine. During the design and debug of a system, the control logic is most susceptible to functional changes and logic errors, making it a leading candidate for Engineering Changes. Any chip change in LSI is next to impossible, resulting in the design of a new chip and a complete scrap of the old chip.

Control logic acts as the interface between a processor's data flow and microcode. Since different processors invariably have different microcode structures, this interface logic is unique and implies low usage. For these reasons, an attempt is made to put as much of this hardware into array logic as possible. This requires a very systematic organization and alignment of the microword structure, which acts as the addressing mechanism for the array logic.

The drawing shows a single LSI chip part which can perform control functions and which is flexible enough to be changed, so that it need not be replaced because of an Engineering Change. This chip will eliminate much of the single usage part numbers and scrap, due to changes in system designs using LSI technology.

One known storage chip proposal does not lend itself to this type of usage, because of the data storage characteristics of a single-bit readout for a nine-bit address (512 x 1). For distributive control, smaller storage arrays (64 x 1) with very flexible addressing becomes much more useful. The figure shows such a chip configuration. Each 32 x 1 or 64 x 1 group of bist...