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Photolithographic Etching Method for Integrated Circuits

IP.com Disclosure Number: IPCOM000080754D
Original Publication Date: 1974-Feb-01
Included in the Prior Art Database: 2005-Feb-27
Document File: 2 page(s) / 58K

Publishing Venue

IBM

Related People

Carr, PE: AUTHOR [+4]

Abstract

In the fabrication of integrated circuits, when etching through a silicon dioxide layer to an underlying metallic line utilizing a positive photoresist process, two problems tend to occur.

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Photolithographic Etching Method for Integrated Circuits

In the fabrication of integrated circuits, when etching through a silicon dioxide layer to an underlying metallic line utilizing a positive photoresist process, two problems tend to occur.

1) The positive photoresist may present some adhesion problems with respect to the silicon dioxide, and

2) The image size may be difficult to control.

It has been found that these problems may be due to light scattering of reflected light from the underlying metallization line, during the exposure of the positive photoresist.

The present method solves these problems utilizing an initial structure as shown in Fig. 1. On an integrated circuit structure comprising a metallic line 10 on integrated circuit substrate 11, covered by silicon dioxide layer 12, a layer of a negative photoresist material 13, such as KTFR*, is deposited beneath the positive photoresist 14 which is to be selectively exposed in etching through silicon dioxide layer 12. Negative photoresist layer 13 is preferably hardened by baking prior to the application of positive photoresist layer 14.

Next, as shown in Fig. 2, by appropriate photolithographic masking techniques, an opening 15 is formed in positive photoresist layer 14 while underlying negative photoresist layer 13 is substantially unexposed. However, during the exposure of layer 14, unexposed layer 13 acts as a protective layer to prevent any light from scattering from the surface of metallization...