Browse Prior Art Database

Double Scanning in Large Scale Integration

IP.com Disclosure Number: IPCOM000080758D
Original Publication Date: 1974-Feb-01
Included in the Prior Art Database: 2005-Feb-27
Document File: 2 page(s) / 34K

Publishing Venue

IBM

Related People

Wong, RC: AUTHOR

Abstract

For large-scale integration design, internal latches may be strung together to form a long string of shift registers to ease the problem of testing and diagnosis. This ensures that system states can be initialized and measured through scanning data in and out of the imbedded latches, but the scanning is time-consuming. This scheme is to double up the rate of scanning with minimal cost of extra hardware.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 93% of the total text.

Page 1 of 2

Double Scanning in Large Scale Integration

For large-scale integration design, internal latches may be strung together to form a long string of shift registers to ease the problem of testing and diagnosis. This ensures that system states can be initialized and measured through scanning data in and out of the imbedded latches, but the scanning is time- consuming. This scheme is to double up the rate of scanning with minimal cost of extra hardware.

The conventional shift register stage consists of a master latch and a slave latch, which are gated by two nonoverlapping clocks, A and B. When clock A is up, datum is input into the master latch. When clock A is down, datum is transferred internally from the master latch to the slave latch, while the input datum into the master latch is being ignored. As in the timing diagram shown in Fig. 2, data is inputted only in the odd time slots (t(1), t(3),. .). The scheme shown here is to use the even time slots to also input data.

Any logic design is divided conceptually into two groups, Group A and Group B, with approximately equal number of latches. The group A shift register is designed in the conventional way. The group B shift register is also designed in the conventional way, except that the roles of clock A and clock B are reversed relative to those in Group A, as indicated in Fig. 1. Thus, the odd time slots are for Group A scan input and the even time slots are for Group B scan input. The only extra hardware is the AN...