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Fabricating Complementary Field Effect Transistor Devices

IP.com Disclosure Number: IPCOM000080760D
Original Publication Date: 1974-Feb-01
Included in the Prior Art Database: 2005-Feb-27
Document File: 3 page(s) / 106K

Publishing Venue

IBM

Related People

Beyer, KD: AUTHOR [+2]

Abstract

In this process, the starting structure is a monocrystalline silicon substrate 10 embodying an N-type dopant and having a P pocket diffused region 12. A thermal SiO(2) layer 14, preferably having a thickness on the order of 100 angstroms, is grown, a layer 16 of Si(3)N(4) having a thickness on the order of 300 angstroms is deposited over layer 14, and a layer 18 of pyrolytic SiO(2) deposited having a thickness on the order of 1600 angstroms. In a single photoresist step, windows 20 and 22 are opened in layer 18 for all source and drain diffusions, as shown in Fig. 1.

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Fabricating Complementary Field Effect Transistor Devices

In this process, the starting structure is a monocrystalline silicon substrate 10 embodying an N-type dopant and having a P pocket diffused region 12. A thermal SiO(2) layer 14, preferably having a thickness on the order of 100 angstroms, is grown, a layer 16 of Si(3)N(4) having a thickness on the order of 300 angstroms is deposited over layer 14, and a layer 18 of pyrolytic SiO(2) deposited having a thickness on the order of 1600 angstroms. In a single photoresist step, windows 20 and 22 are opened in layer 18 for all source and drain diffusions, as shown in Fig. 1.

As indicated in Fig. 2, the Si(3)N(4) of layer 16 and the SiO(2) of layer 14 is removed and openings 20 and 22 by dip etching in suitable etchants. The exposed surface of substrate 10 is then oxidized, forming layers 24 and 26 of approximately 800 angstroms in the source and drain windows. A layer 28 is deposited at approximately 470 degrees C over the N-channel source and drain windows, having a thickness of approximately 5000 angstroms. A blockout masking step is used to remove the photoresist over the P-channel area. In an etching step in ten to one buffered HF, the arsenic doped oxide layer 28 is removed over the P-channel area without attacking the layer 24 of thermally grown oxide. This etching process can be achieved, because the etching rate of arsenosilicate glass deposited at 470 degrees C is five times faster than the etch rate of thermally grown SiO(2).

Arsenic is diffused into substrate 10 forming source and drain regions 30 and 32, by heating at 1050 degrees C for 90 minutes. The arsenic diffuses through the layer 26 into the silicon and the layer 24 over the P-channel window increases to approximately 2,000 angstroms. After diffusion, the arsenic doped oxide and the oxide in the P-channel source and drain area are removed in a P etch, which etches the arsenic doped oxide about three times fa...