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On Chip Engineering Change Method

IP.com Disclosure Number: IPCOM000080773D
Original Publication Date: 1974-Feb-01
Included in the Prior Art Database: 2005-Feb-27
Document File: 2 page(s) / 33K

Publishing Venue

IBM

Related People

Cass, EE: AUTHOR [+2]

Abstract

With the ever increasing complexity of integrated circuit chips in the direction of "Computer-On-A-Chip", integrated circuit chips are becoming more and more specialized, i.e., the chip embodies a function of a subfunction of a system. Where formerly, the prevalent approach in the art was to produce a master chip which could be tailored to perform a wide variety of circuit functions, the present and future tendency appears to be more and more in the direction of designing each chip specifically for a particular function. Therefore, the number of specific chip layouts which have to be designed for each particular system has been greatly multiplied. As a result, turn around time and development time for specific chips have been minimized.

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On Chip Engineering Change Method

With the ever increasing complexity of integrated circuit chips in the direction of "Computer-On-A-Chip", integrated circuit chips are becoming more and more specialized, i.e., the chip embodies a function of a subfunction of a system. Where formerly, the prevalent approach in the art was to produce a master chip which could be tailored to perform a wide variety of circuit functions, the present and future tendency appears to be more and more in the direction of designing each chip specifically for a particular function. Therefore, the number of specific chip layouts which have to be designed for each particular system has been greatly multiplied. As a result, turn around time and development time for specific chips have been minimized. Designers will no longer have the luxury of a great amount of time in which to effect an engineering change.

In view of this background, the present method provides an approach whereby engineering changes to correct design defects which are first discovered after the chip has been fabricated and tested, may be made directly on the chip without the necessity and time delay of scrapping the particular chip. In accordance with the present approach, all unused areas on a chip are filled with extra or redundant circuit units or cells. In addition, all unused portions of wiring channels on the chip are filled with extra lengths of wiring. Then, when an engineering change is necessitated by a design defe...