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Browse Prior Art Database

Wafer Structure Permitting Distribution from the Back Side of the Wafer

IP.com Disclosure Number: IPCOM000080775D
Original Publication Date: 1974-Feb-01
Included in the Prior Art Database: 2005-Feb-27
Document File: 2 page(s) / 55K

Publishing Venue

IBM

Related People

Wu, LL: AUTHOR

Abstract

Because of the general trend in the semiconductor integrated circuit art towards larger chips, and even a single chip on a wafer, distribution of power poses a problem. A structure and method for forming the wafer is provided wherein distribution is made from power lines on the back of the wafer, thereby freeing more "real estate" on the front or active side of the wafer.

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Wafer Structure Permitting Distribution from the Back Side of the Wafer

Because of the general trend in the semiconductor integrated circuit art towards larger chips, and even a single chip on a wafer, distribution of power poses a problem. A structure and method for forming the wafer is provided wherein distribution is made from power lines on the back of the wafer, thereby freeing more "real estate" on the front or active side of the wafer.

In accordance with the present structure, power from the back side of the wafer is brought through an opening in the wafer to the front side of the wafer, so that power can be uniformly distributed.

Commencing with a silicon substrate 10 and using a silicon nitride mask which is adhered to substrate 10 by an intermediate silicon dioxide layer, an opening 11 is etched into the silicon dioxide using a conventional silicon dioxide etchant. Oxide is regrown over the surface and a silicon nitride layer is deposited over the silicon dioxide, to provide silicon dioxide-silicon nitride composite layer 12, Fig. 1. A highly doped polycrystalline silicon layer 13 is grown over the structure, Fig. 2. Then, powered by mechanical polishing, the layer 13 of polysilicon is removed leaving the polysilicon pocket 14 shown in Fig. 3. This surface is covered by a silicon dioxide-silicon nitride composite layer 15, which is formed over the pocket 14.

Next, as shown in Fig. 4, a trench 16 is etched from the back side of the wafer to polysilicon p...