Browse Prior Art Database

Ion Implanted Polycrystalline Silicon FET Gates

IP.com Disclosure Number: IPCOM000080777D
Original Publication Date: 1974-Feb-01
Included in the Prior Art Database: 2005-Feb-27
Document File: 1 page(s) / 11K

Publishing Venue

IBM

Related People

Hornung, A: AUTHOR [+3]

Abstract

Silicon gates on field-effect transistors (FET's) are fabricated by depositing polycrystalline silicon on the gate insulating material, and then introducing sufficient impurity into the polysilicon to lower its sheet resistance, so that voltage drops and contact resistances are minimized. In cases where topology considerations limit the thickness of the polysilicon to the order 2,000 angstroms or less, the use of a diffusion process for introducing the gate impurity adversely effects device yield and reliability. The diffusion conditions for obtaining low-sheet resistivity cause the impurity to penetrate through thin polycrystalline silicon gates, into the underlying insulating layer.

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Ion Implanted Polycrystalline Silicon FET Gates

Silicon gates on field-effect transistors (FET's) are fabricated by depositing polycrystalline silicon on the gate insulating material, and then introducing sufficient impurity into the polysilicon to lower its sheet resistance, so that voltage drops and contact resistances are minimized. In cases where topology considerations limit the thickness of the polysilicon to the order 2,000 angstroms or less, the use of a diffusion process for introducing the gate impurity adversely effects device yield and reliability. The diffusion conditions for obtaining low- sheet resistivity cause the impurity to penetrate through thin polycrystalline silicon gates, into the underlying insulating layer.

Low-sheet resistivity is achieved in thin polycrystalline silicon FET gates by ion implanting arsenic at a depth of approximately half the thickness of the gate or less, and then annealing at a temperature and for a time sufficient to remove damage, without causing the implanted arsenic to penetrate the polysilicon-gate insulator interface. The annealing is carried out at temperatures of about 900 degrees C and below, which produces inconsequential spreading of the ion implanted arsenic impurity profile in the polysilicon gate.

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