Browse Prior Art Database

Badge Reading System with Integral Status Monitoring

IP.com Disclosure Number: IPCOM000080788D
Original Publication Date: 1974-Feb-01
Included in the Prior Art Database: 2005-Feb-27
Document File: 2 page(s) / 38K

Publishing Venue

IBM

Related People

Bigbie, SE: AUTHOR [+2]

Abstract

This logic circuitry permits a high-priority source of discrete data records to share a common transmission line with a source of low-priority random data.

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Badge Reading System with Integral Status Monitoring

This logic circuitry permits a high-priority source of discrete data records to share a common transmission line with a source of low-priority random data.

Badge reader 20 is the highest priority data source and condition detecting switch 37, in a controlled access application, is the lower priority source. Switch 35, when closed by the leading edge of badge 40, fires single-shot 26 signalling that a data record block is ready for transfer. Switch 36 detects an end of record from badge 40. When latch 27 turns on, its output 27A fires single-shot 29 and brings up one leg of AND 23, allowing data read by head 21 on badge 40 and amplified by amplifier 22 to be passed through OR 24 into driver 25. Output 27B prevents the condition of latch 33 from reaching OR 24.

If the leading edge of badge 40 reaches switch 36 before single-shot 29 times out, then latch 27 is reset by switch 36 through OR 28. Latch 27 is reset by single-shot 29, inverter 30 and single-shot 31 if badge 40 has not previously reached switch 36. Single-shots 29 and 31 prevent the undesirable condition that badge 40 is left in reader 20, or moved back and forth without being removed from reader 20. The time out of single-shot 29 has a length sufficient to allow complete reading of any badge 40 at a specified speed. Single-shot 26 insures that badge 40 must be withdrawn and reinserted to start another read cycle.

The random data of condition detecting...