Browse Prior Art Database

Complete Half Wave Thyrister Control

IP.com Disclosure Number: IPCOM000080814D
Original Publication Date: 1974-Feb-01
Included in the Prior Art Database: 2005-Feb-27
Document File: 2 page(s) / 40K

Publishing Venue

IBM

Related People

Van Cleave, GW: AUTHOR [+2]

Abstract

A voltage control circuit includes a primary power line 10 including a load lamp 11 in series with triac 12. Voltage is sensed across load 11 by circuit 13, resulting in a current flow difference between transistors 14 and 15 proportional to RMS voltage error, as described in U.S. Patent 3,746,970. This error-representing-current difference is available at point 16 to charge or discharge error integrating capacitor 17.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 100% of the total text.

Page 1 of 2

Complete Half Wave Thyrister Control

A voltage control circuit includes a primary power line 10 including a load lamp 11 in series with triac 12. Voltage is sensed across load 11 by circuit 13, resulting in a current flow difference between transistors 14 and 15 proportional to RMS voltage error, as described in U.S. Patent 3,746,970. This error- representing-current difference is available at point 16 to charge or discharge error integrating capacitor 17.

Zero crossing detector circuit 18 is connected through transformer 19 across input power line 10 to develop a gating pulse 20, coincident with zero crossing of the sinusoidal power applied to line 10. The charge on capacitor 17 is compared with a threshold level in circuit 21; and if over the threshold level, a demand signal is delivered to AND circuit 22. The pulse 20 from zero crossing detector 18 is also applied to the AND circuit 22 to gate the demand signal to triac 12, at a time when the AC power is crossing zero voltage.

1

Page 2 of 2

2

[This page contains 2 pictures or other non-text objects]