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Floating Point Representation

IP.com Disclosure Number: IPCOM000080818D
Original Publication Date: 1974-Feb-01
Included in the Prior Art Database: 2005-Feb-27
Document File: 4 page(s) / 87K

Publishing Venue

IBM

Related People

Melkun, BF: AUTHOR

Abstract

This description provides means for hexadecimal floating-point numbers to be handled by an electronic computer system to avoid the need for half-byte shifting to align mantissas, when using a common computer format for a floating-point number of the type shown in Fig. 1. In Fig. 1, the floating-point number consists of the sign S, exponent (i.e., characteristic) X, and the mantissa (i.e., fraction) M. The length of the format in Fig. 1 is 4, 8 or 16 bytes, in which only the mantissa has a size variation, i.e., 3, 7 or 14 bytes. Each byte in the mantissa contains two hexadecimal numbers, i.e., the mantissa comprises 6, 14 or 28 numbers, respectively.

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Floating Point Representation

This description provides means for hexadecimal floating-point numbers to be handled by an electronic computer system to avoid the need for half-byte shifting to align mantissas, when using a common computer format for a floating- point number of the type shown in Fig. 1. In Fig. 1, the floating-point number consists of the sign S, exponent (i.e., characteristic) X, and the mantissa (i.e., fraction) M. The length of the format in Fig. 1 is 4, 8 or 16 bytes, in which only the mantissa has a size variation, i.e., 3, 7 or 14 bytes. Each byte in the mantissa contains two hexadecimal numbers, i.e., the mantissa comprises 6, 14 or 28 numbers, respectively.

To do a conventional floating-point operation such as `Add', the mantissas of the operands must be aligned in relation to the same exponent for both numbers. In particular, if the exponents are different, one of the operands must be half-byte shifted for each unit difference in the exponents. Thus the larger exponent is decremented by one per right-digit shift of the mantissa until the exponents are equal. Alternatively, the smaller exponent may be incremented by one per left- digit shift of the mantissa until the exponents are equal.

The half byte conventional shifting can be avoided by the following method which allows whole byte shifting. It does this by initially adjusting the mantissas so that both exponents are made even numbers. Then whole byte shifts of the mantissa can be used, since whole byte shifts increment the exponent to the next even number.

Fig. 2 shows in detail the half-byte hexadecimal components in the mantissa M, and X(L) is the lowest order bit in the exponent X.

If the low-order bit X(L) is 1, then the exponent is odd, and the mantissa is adjusted to comprise the sequence: m(1B), m(2), .... m(n), M(1A). If the low-order bit X(L) is 0, the exponent is even, and mantissa remains with its sequence: M(1A), m(1B), m(2), ..., m(n).

This provides stability in the positions of bytes m(2) to m(n), and at most only the first and last bytes are changed.

Fig. 3A illustrates hardware for converting from the "external" form shown in input register 7, to the "internal" form shown in output register 8. In the internal form, X(L) is always 0. The in...