Browse Prior Art Database

Multiplex Processor

IP.com Disclosure Number: IPCOM000080852D
Original Publication Date: 1974-Feb-01
Included in the Prior Art Database: 2005-Feb-27
Document File: 3 page(s) / 61K

Publishing Venue

IBM

Related People

Oblonsky, JG: AUTHOR

Abstract

An improvement in the multijob stream environment is achieved by allowing a plurality of instruction streams to share a cache and an integrated pipeline, as shown in Fig. 1. A more detailed description of the system is illustrated in Fig. 2.

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Multiplex Processor

An improvement in the multijob stream environment is achieved by allowing a plurality of instruction streams to share a cache and an integrated pipeline, as shown in Fig. 1. A more detailed description of the system is illustrated in Fig. 2.

The Instruction Address Loop 1 has the I-address array 101, three I-address buffer states 201, 301 and 401, and the I-address update stage 501. The I- address array 101 contains eight updated addresses of the next instruction for each of the right instruction streams, together with some control information, e.g., whether the instruction is a pseudo-operation. Under the control of the stream selector 1000, the I-address array 101 sends the selected instruction address both to the I-buffer 211 in the Instruction Loop 2 and to the I-address buffer stage 201.

After passing through the buffer stages 201, 301 and 401, the instruction address is updated in the update stage 501 with respect to the associated instruction length and its position in the I-buffer 211. If required, an I-fetch request is generated and sent to the I-fetch request stack 5000. If the current instruction is a successful branch, its address is replaced in stage 501 by the target address from the output 4210 of the address adder 421. The target address is not updated in stage 501 but an I-fetch request may be generated.

The Instruction Loop 2 consists of the I-buffer array 211, I-register 311 and two pseudo-instruction generator stages 411 and 511, and execution control stages 611, 711, 811 and 911. The I-buffer array 211 contains 2 blocks (4 doublewords per block) of instructions for each of the eight instruction streams. The instruction blocks are loaded into the I-buffer array 211 from the cache 621 under the control of the I-fetch request stack 5000 (the required data and control paths are not shown in Fig. 1).

The decoded control part of the instruction follows into the stages 411 and 511 of the pseudo-instruction generator and control stages 711 through 1011. In the pseudo-instruction generator, a pseudo-instruction is created for those instructions, which cannot be completed by one pass through the execution loops 3 or 4. If a pseudo-instruction is created in stage 511, it is returned to the I-buffer array 211. The stages 311 through 1011 control also the execution of the instructions in the corresponding stages of the execution loops 3 and 4. (The necessary control lines are not shown in Fig. 2.)

The Floating-Point Execution Loop 4 consists of three sets of floating register (FLR) arrays 561, 662 and 663; preshift stages 762 and 763; adder stage 860 and postshift stage 960.

A typical floating-point instruction uses the facilities of the loop 3 to generate the address and to get one operand from cache 621 into the preshift stage 762. The second operand is obtained from the FLR array 663.

The multiply/divide cycling unit (9000) contains circuits to generate the product (or quotient) in the sum/carry form...