Browse Prior Art Database

Josephson Tunneling Device Shift Register

IP.com Disclosure Number: IPCOM000080853D
Original Publication Date: 1974-Feb-01
Included in the Prior Art Database: 2005-Feb-27
Document File: 3 page(s) / 41K

Publishing Venue

IBM

Related People

Yao, YL: AUTHOR

Abstract

A shift register is a logic element which consists usually of many stages of identical storage elements connected in a series fashion, which is capable of storing information and, upon a command, is able to shift the information from one stage to an adjacent stage.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 55% of the total text.

Page 1 of 3

Josephson Tunneling Device Shift Register

A shift register is a logic element which consists usually of many stages of identical storage elements connected in a series fashion, which is capable of storing information and, upon a command, is able to shift the information from one stage to an adjacent stage.

A shift register stage which consists of two Josephson Tunneling Devices (JTD), is shown in Fig. 1. In order to describe the operation of the shift register, the basic characteristics of a JTD should be understood. A JTD has two distinct states as shown in Fig. 2. State "A" which has no voltage drop across the junction may be defined as a logic "0" and the state "B" which has a voltage drop across the junction (2 delta V) may be defined as a logic "1". Assume (referring to Fig. 1) that a device in the 0 state switches to the 1 state only when the proper gate current (e.g. I1) is applied, and when both the control current (e.g., IC1) and the input current (Iin) are applied. Either the control current or the input current alone will not switch the device. Further, a device in the 1 state will not switch to the 0 state unless the gate current is dropped to zero momentarily, provided the control current and the input current are not both present.

The operation of the shift register as shown in Fig. 3 can now be described. The first two stages of a multistage shift register with their associated timing waveforms are shown in Fig. 3. Currents I1, I2, ICl and IC2 are all current sources.
1. Assume all devices (Q1-Q4) are initially in the 0 state.
2. During time period T1, gate current I1 drops to zero and

the

device Q1 and Q2 switch to the 0 state (if they are not in the

0 state).
3. During time T2, control current IC1 is applied. Assume

that

during this time the input current (Iin) is present, the device

will switch to the 1 state. The voltage developed across the

junction will produce an output current, as determined by the

value of Ro. However, Q2 will not swi...