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# High Speed, Wide Margin, Logic Family

IP.com Disclosure Number: IPCOM000080859D
Original Publication Date: 1974-Feb-01
Included in the Prior Art Database: 2005-Feb-27
Document File: 3 page(s) / 44K

IBM

## Related People

Herrell, DJ: AUTHOR

## Abstract

A high-speed, wide-margin, logic family capable of operation at high speed including OR-NOT-NOR logic circuits which are self-resetting, is described.

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High Speed, Wide Margin, Logic Family

A high-speed, wide-margin, logic family capable of operation at high speed including OR-NOT-NOR logic circuits which are self-resetting, is described.

Referring now to Fig. 1, there is shown therein a Josephson circuit having impedance levels, which permit self-resetting of the Josephson device J1. Device J1 has a configuration characterized as a double junction cross control and has a gain curve as shown in Fig. 2. The double junction J1 provides wide margins for logic applications and speeds up the self-resetting logic via the gap voltage of 4 delta.

For self-resetting, the following conditions must be ensured: 4 delta over R > I
(1) 2R(J) over R > I over I(min) (2) and I(R) < V(min) (3) Conditions (2), (3) are necessary for self-resetting.

For the circuit of Fig. 1, the time constant tau for the output current signal i(t) is given approximately by tau = 2 lo Do Zo over R (4) wherein lo = length of output lines Do = Delay/unit length Zo = Characteristic impedance.

When the double junction J1 switches to the V not = 0 state under the influence of control circuitry C1, the rise time t(r) of i(t) can be estimated as follows: where t(r) over tau approx. = I over 4 delta/R then t(r) = I over 2 delta lo Do Zo (5)

When the voltage and current for the double junction J1 falls below V(min), I(min), the voltage latches back to V = 0 and the reset condition is initiated. Resetting proceeds with the same time constant tau. A fall time of approximately 2 tau is followed by an oscillation time of approximately 2 tau, giving a total reset time of 4 tau.

Entering typical values into equations (4), (5) demonstrates the high-speed potential of the arrangement of Fig. 1.

Using SiO (epsilon = 5.5) of 1000 angstroms thickness for ground plane insulation, one obtains: Zo = 1.13 over...