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Field Alterable Redundancy for Dynamically Ordered Block Oriented Memory

IP.com Disclosure Number: IPCOM000080880D
Original Publication Date: 1974-Feb-01
Included in the Prior Art Database: 2005-Feb-27
Document File: 2 page(s) / 48K

Publishing Venue

IBM

Related People

Walker, EL: AUTHOR

Abstract

This structure provides redundancy for a memory which is comprised of dynamically ordered shift registers (DOSR) arranged in block orientation. The chip organization of the memory is shown in Fig. 1, in which a plurality of dynamically ordered shift registers DOSR 1... DOSR M are located on the memory chip 10. A conventional register (I/O REG) is used for I/O functions. Redundancy is implemented using the additional defect personalization shift register (DPSR).

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Field Alterable Redundancy for Dynamically Ordered Block Oriented Memory

This structure provides redundancy for a memory which is comprised of dynamically ordered shift registers (DOSR) arranged in block orientation. The chip organization of the memory is shown in Fig. 1, in which a plurality of dynamically ordered shift registers DOSR 1... DOSR M are located on the memory chip 10. A conventional register (I/O REG) is used for I/O functions. Redundancy is implemented using the additional defect personalization shift register (DPSR).

DPSR carries the defect personalizations for the DOSRs (the I/O register is assumed to be good), and is oriented such that the read/write functions are 180 degrees out of phase with these functions for the I/O register. Therefore, the controls to the two registers DPSR and I/O REG are commoned.

The specific defect personalization of a chip 10 is determined by the presence of 1's or 0's in the DPSR. For example, if DOSR 3 has been determined to be defective, the DPSR would have 1's written into its third position and 0's in the remaining bit locations prior to loading data from the DOSR's, or after repeated errors from DOSR 3. The significant of the 1 written into the DPSR is that this causes a signal to appear at the bit-out line 180 degrees ahead of the data. This signal is then used to inhibit the bit-out line during data time (phi(4)) (Fig. 2), while concurrently enabling a redundant chip.

Fig. 2 shows one way that this redundancy...