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Asymmetrical Oscillator Circuit

IP.com Disclosure Number: IPCOM000080888D
Original Publication Date: 1974-Feb-01
Included in the Prior Art Database: 2005-Feb-27
Document File: 2 page(s) / 29K

Publishing Venue

IBM

Related People

DeMario, G: AUTHOR

Abstract

This asymmetrical oscillator circuit consists of an oscillator 10 which provides oscillations of substantially sinusoidal character, as signal pattern A; a phase-shifting network 12 having any output signal B with a predetermined phase shift relative to signal A; a first limiter 14 connected directly to receive the signal A and produce signal C; a second limiter 16 connected to receive the phase-shifted output of unit 12 and produce signal D; and an OR gate 18 connected to receive the output signals C and D of limiters 14 and 16, to produce the signal E as the oscillator circuit output.

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Asymmetrical Oscillator Circuit

This asymmetrical oscillator circuit consists of an oscillator 10 which provides oscillations of substantially sinusoidal character, as signal pattern A; a phase-shifting network 12 having any output signal B with a predetermined phase shift relative to signal A; a first limiter 14 connected directly to receive the signal A and produce signal C; a second limiter 16 connected to receive the phase-shifted output of unit 12 and produce signal D; and an OR gate 18 connected to receive the output signals C and D of limiters 14 and 16, to produce the signal E as the oscillator circuit output.

The rise of signal C at time t1 causes output E to rise. Prior to the fall of signal C, phase-shifted signal D rises and is up when signal C falls, thus sustaining the output signal E until time t2 when signal D falls.

The duration of signal E can be varied by varying the amount of phase shift between signals A and B. This circuit provides precise timing of transitions, particularly at high frequencies. Tolerances on the components of the phase- shift network 12 may be +/- 10% and still provide a tight tolerance duty factor.

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