Browse Prior Art Database

Selective Receive Control for a Terminal

IP.com Disclosure Number: IPCOM000080900D
Original Publication Date: 1974-Mar-01
Included in the Prior Art Database: 2005-Feb-27
Document File: 2 page(s) / 31K

Publishing Venue

IBM

Related People

VandenBerg, JW: AUTHOR [+2]

Abstract

When an intelligent programmable terminal is attached to a multiterminal communications network, the processing power of the terminal is frequently used to do the line control procedures such as bit assembly, character assembly and control character decoding, thereby reducing the hardware costs of the line adapter. The processing is done by the use of interrupts, which will shift the processor from its regular program to process the interrupt condition and then return to the regular program. In the small microprocessors used for the terminals of a network, this kind of interrupt will be entered for each bit of data on the network whether the data is for the receiving terminal or not.

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Selective Receive Control for a Terminal

When an intelligent programmable terminal is attached to a multiterminal communications network, the processing power of the terminal is frequently used to do the line control procedures such as bit assembly, character assembly and control character decoding, thereby reducing the hardware costs of the line adapter. The processing is done by the use of interrupts, which will shift the processor from its regular program to process the interrupt condition and then return to the regular program. In the small microprocessors used for the terminals of a network, this kind of interrupt will be entered for each bit of data on the network whether the data is for the receiving terminal or not. The extensive amount of processing interruptions due to data for another terminal, results in a serious reduction in the processing capacity of the terminal.

In this method, the transmission of interrupt signals on a line 1 from the line adapter 2 of a terminal 3 to the processor 4, is gated by a gate 5. The gate 5 is opened to pass the signal on line 1 when a latch 6 is set to energize the other input line 7 to gate 5. The latch 6 will be set when a carrier detect line 8 of the line adapter 2 is deenergized to signal that there is no data being transmitted across communications line 9, and will be reset to a state to block gate 5 by a signal on line 10 from the processor 4.

In normal procedures, the processors 4 of all terminals 3 will be int...