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Browse Prior Art Database

Bulk Access Surface Storage Memory Cells

IP.com Disclosure Number: IPCOM000080919D
Original Publication Date: 1974-Mar-01
Included in the Prior Art Database: 2005-Feb-27
Document File: 3 page(s) / 55K

Publishing Venue

IBM

Related People

Noble, WP: AUTHOR

Abstract

Each of the memory cells of an array is defined by the area at the intersection of two silicon lines, separated by a metallurgical junction, wherein one line is the bit line and the other the word line of the cell. The storage node of the cell is a metal-oxide-semiconductor (MOS) capacitor formed between an alternating current ground plane and an inversion layer formed on the p-type silicon of the word line.

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Bulk Access Surface Storage Memory Cells

Each of the memory cells of an array is defined by the area at the intersection of two silicon lines, separated by a metallurgical junction, wherein one line is the bit line and the other the word line of the cell. The storage node of the cell is a metal-oxide-semiconductor (MOS) capacitor formed between an alternating current ground plane and an inversion layer formed on the p-type silicon of the word line.

In Fig. 1 a memory array having four cells is illustrated in a plan view. Fig. 2 is a cross-sectional view of the array shown in Fig. 1 taken through line 2-2, Fig. 3 is a cross-sectional view of the array shown in Fig. 1 taken through line 3-3, and Fig. 4 shows a pulse program which may be used with the cells. The array includes a p-type silicon substrate 10 supporting single-crystal n-type silicon bit lines 12 and a first insulating layer of, e.g., silicon dioxide 14 disposed between bit lines 12. Word lines 16 made of silicon are arranged orthogonal to bit lines 12 and form a metallurgical junction 18 with bit lines 12 at the intersection of the lines 12, 16. Silicon word lines 16 include single-crystal p-type silicon segments 15, formed over the single-crystal n-type bit lines 12 and polycrystalline silicon segments 17 interconnecting the single-crystal p-type silicon segments 15. A second insulation layer of, e.g., silicon dioxide 20 is disposed between word lines
16. Storage nodes 22 are provided over each metallurgical junction 18 as MOS capacitors, formed by alternating current ground plane 24 and single-crystal p- type silicon segments 15 with a third insulating layer of, e.g., silicon dioxide 26 interposed therebetween.

Word line driver circuits 28 are connected to word lines 16 which are suitably terminated by appropriate impedances 30, and bit line driver and sense amplifier circuits 32 are connected to bit lines 12 which are suitably terminated by appropriate impedances 34. Ground plane 24 is held at an appropriate DC reference potential, e.g., +5 volts, by a bias source 36.

Voltage conditions for providing hold, rend, write 1 (W1) and write 0 (W0) states at a given cell are as follows:

Hold: A reverse bias is created between word and bit lines 12, 16 with the word line 16 being at ground potential and the hit line 12 being at +7 volts. The word line 16 to ground plane 24 potential provides, in p-type silicon segment 17, a surface space-charge condition of either deep depletion or inversion with ground plane 24 having a DC bias of +5 volts.

Read: The bit line 12 potential is held at +7 volts and the word line 16 to ground plane voltage differential is eliminated, by bringing...