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Matrix Bit Packing Circuit

IP.com Disclosure Number: IPCOM000080944D
Original Publication Date: 1974-Mar-01
Included in the Prior Art Database: 2005-Feb-27
Document File: 3 page(s) / 42K

Publishing Venue

IBM

Related People

Dunham, GF: AUTHOR

Abstract

The arrangement shown in Fig. 1 illustrates the manner in which standardized circuit module, configured to provide a data shift register, may be arranged with suitable external connections to provide for carrying out logical operations on the outputs of the shift register, without disturbing data in other positions of the shift register.

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Matrix Bit Packing Circuit

The arrangement shown in Fig. 1 illustrates the manner in which standardized circuit module, configured to provide a data shift register, may be arranged with suitable external connections to provide for carrying out logical operations on the outputs of the shift register, without disturbing data in other positions of the shift register.

In the arrangement shown, five shift register positions are provided, each including a flip-flop or bistable element designated by the reference character FF followed by the postscripts A, B, C, D and E for the five consecutive positions. It will be noted that a data information line is provided to the input on one side of shift register FFA on a line DI. The output from register FFA is supplied as an input to FFR, and this configuration is carried through all five stages of the shift register to and including the element FFE, which provides an output therefrom on a data output line DO. Preset signals to the five stages of the shift register are supplied on lines PA through PE, constituting the presetting lines for the various stages. These inputs are supplied to the associated shift register only when a preset enable pulse is applied to a common preset enable line PR, which enables a conventional AND circuit in the input side of each of the shift register stages.

The relationship between the clock pulses which are supplied on a common clock line CL to each of the shift register stages in the module and the preset enable pulse which controls the supply of individual presetting pulses via the line PR, is illustrated in the waveform diagram of Fig. 2. It will be noted also that a negative-going reset pulse is supplied at a time at approximately the center of the preset enable pulse. This reset pulse is supplied to all of the stages of the register via a common reset line CR.

The outputs from the various stages of the shift register are present on the output lines such as OA through OE. The signals on these output lines are fed back under the control of external logic, when necessary, to the individual input lines such as PA through PE. For example, stage A of the register has an output line OA which, as can be seen from the drawing, is connected in regenerative fashion to the input line PA by a connection external to the module. The output line OB from stage B is supplied to one input of an OK circuit 3, the other input being provided with a setting pulse SB, the output of OR circuit 3 supplying one input of an AND circuit 5, the other line of which is a signal line designated as RB. With line RB appropriately energized, a signal on line OB or SB will be supplied via the AND circuit to the input line PB.

Line OC is connected to one input of an OR circuit 7, the other input of which is a signal SC, and the output...