Browse Prior Art Database

Integrated Circuits Incorporating Complementary FET Devices

IP.com Disclosure Number: IPCOM000080961D
Original Publication Date: 1974-Mar-01
Included in the Prior Art Database: 2005-Feb-27
Document File: 2 page(s) / 35K

Publishing Venue

IBM

Related People

Anantha, NG: AUTHOR [+2]

Abstract

In this process, wafer 10 of N-type silicon is thermally oxidized. Openings are etched in the resultant oxide layer to define the ultimate N and P type regions, and the oxide masking layer used to selectively etch the silicon to form wells 12 and 14, as shown in Fig. 1. The surface face of body 10 is then oxidized to form layer 16, as shown in Fig. 2. Opening 18 is made in the bottom of well 12 and a P type impurity introduced, forming region 20. As shown in Fig. 3, an opening 22 is made in layer 16 to expose the bottom surface of well 14. An N- type epitaxial layer having a resistivity of approximately 2 ohm/cm is then grown in wells 12 and 14.

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Integrated Circuits Incorporating Complementary FET Devices

In this process, wafer 10 of N-type silicon is thermally oxidized. Openings are etched in the resultant oxide layer to define the ultimate N and P type regions, and the oxide masking layer used to selectively etch the silicon to form wells 12 and 14, as shown in Fig. 1. The surface face of body 10 is then oxidized to form layer 16, as shown in Fig. 2. Opening 18 is made in the bottom of well 12 and a P type impurity introduced, forming region 20. As shown in Fig. 3, an opening 22 is made in layer 16 to expose the bottom surface of well 14. An N- type epitaxial layer having a resistivity of approximately 2 ohm/cm is then grown in wells 12 and 14.

In well 12, containing the P diffused region 20, the epitaxial silicon will be P type by outdiffusion. In well 14, the impurity remains N type. The surface of the device is then lapped and polished and a layer 24, approximately 2,000 angstroms in thickness is formed over the silicon in wells 12 and 14, as shown in Fig. 4. N type regions 26 in the P region 28 and also region 30 for ultimately insuring only contact to the substrate are diffused, using standard oxide mask and diffusion techniques.

P + diffusions 32 are formed in region 34. The gate insulation and metallurgy is then deposited utilizing conventional techniques.

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