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Device for Keyboard Bounce Treatment

IP.com Disclosure Number: IPCOM000080974D
Original Publication Date: 1974-Mar-01
Included in the Prior Art Database: 2005-Feb-27
Document File: 3 page(s) / 47K

Publishing Venue

IBM

Related People

Marijon, JL: AUTHOR

Abstract

Shown is logic circuitry for handling the pulse response of a keyboard, in order to reject the parasites and detect the true depression of a key.

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Device for Keyboard Bounce Treatment

Shown is logic circuitry for handling the pulse response of a keyboard, in order to reject the parasites and detect the true depression of a key.

The output level produced upon the depression of a key in a keyboard having no specific means for reducing bounce is as represented in Fig. 1a. When the key is depressed, the switch is ON and the output level is high and when the key is released the switch is OFF and the output level is low. The key is taken into account as soon as a positive pulse having a duration exceeding t1 appears, the positive bounces preceding this pulse are rejected as parasites.

After the appearance of this pulse, each negative pulse is a defect and has a limited duration. Consequently the key is detected as released when a low level having a duration exceeding t2 occurs.

In a specific embodiment t1 is chosen equal to four milliseconds and t2 is chosen equal to twenty milliseconds. Consequently the minimum delay between depressing two keys is t = t1 t2, and the maximum keying speed is 1/t which gives in the chosen example forty one-key depressions per second.

The logic circuitry for detecting these duration conditions is represented on Fig. 1b. The pulses produced by a key depression are applied on line 1. The circuitry essentially comprises a counter 2 having a clock input C2 and a reset input R2, giving output signals on line +4 and on line +20 when it has counted four milliseconds and twenty milliseconds, respectively, under the control of a clock.

The operations of counter 2 are controlled by a logic arrangement of an exclusive OR circuit 3, OR circuit 4, AND circuits 5, 6 and 7 and D-type flip-flops 8 and 9.

Flip-flops 8 and 9 have inputs...