Dismiss
InnovationQ will be updated on Sunday, Oct. 22, from 10am ET - noon. You may experience brief service interruptions during that time.
Browse Prior Art Database

Serial Data Clock Control

IP.com Disclosure Number: IPCOM000081014D
Original Publication Date: 1974-Mar-01
Included in the Prior Art Database: 2005-Feb-27
Document File: 2 page(s) / 54K

Publishing Venue

IBM

Related People

George, GA: AUTHOR

Abstract

Data clocking control with noise rejection is derived from transitions in a data signal. At CLOCK IN time, relatively asynchronous input signal DATA IN is sampled into the four-stage shift register, composed of triggers T1, T2, T3 and T4. CLOCK IN also advances the counter consisting of trigger stages TA, TB, TC and TD, when the RESET line is inactive (i.e. when all shift register stages have identical conditions). When the count reaches a predetermined state (1XX1) DATA CLOCK line is pulsed, providing control synchronous with DATA IN to sampling input of buffer output trigger stage TS (to store the all 1's or all 0's state then contained in shift register T1-T4), and to external circuitry communicating with TS.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 88% of the total text.

Page 1 of 2

Serial Data Clock Control

Data clocking control with noise rejection is derived from transitions in a data signal. At CLOCK IN time, relatively asynchronous input signal DATA IN is sampled into the four-stage shift register, composed of triggers T1, T2, T3 and T4. CLOCK IN also advances the counter consisting of trigger stages TA, TB, TC and TD, when the RESET line is inactive (i.e. when all shift register stages have identical conditions). When the count reaches a predetermined state (1XX1) DATA CLOCK line is pulsed, providing control synchronous with DATA IN to sampling input of buffer output trigger stage TS (to store the all 1's or all 0's state then contained in shift register T1-T4), and to external circuitry communicating with TS.

The timing of the foregoing circuit operations is indicated in Fig. 2. The frequency of CLOCK IN is at least three times the maximum transition frequency of DATA IN.

Obviously, with a longer shift register pipeline the sensitivity to DATA IN noise can be reduced. Additional noise insensitivity can be achieved by combining voting circuits with a longer shift pipeline.

When there is no DATA IN noise, each DATA IN transition is accompanied by a reversed entry in the shift register and activation of the counter RESET line. Thereafter, the count advances in step with the reversed entry shift, so that the DATA CLOCK line is pulsed at a predetermined time after the transition. However, if noise is present in DATA IN, giving rise to a re...