Browse Prior Art Database

Reconfigurable Machine

IP.com Disclosure Number: IPCOM000081016D
Original Publication Date: 1974-Mar-01
Included in the Prior Art Database: 2005-Feb-27
Document File: 3 page(s) / 46K

Publishing Venue

IBM

Related People

Fleisher, H: AUTHOR [+2]

Abstract

In order to maintain advantages of partitioning input variables into groups of two inputs each, when implementing system functions in array logic networks employing partitioned input decoding, it is desirable to preserve the redundancy and reconfigurability capabilities inherent in array logic structures. It is also desirable to maintain a flexibility of interconnection among communicating array logic structures, so that interrelated engineering changes in a network of array structures may be accommodated, without resorting to the difficult and expensive expedient of inserting "yellow" wires.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 52% of the total text.

Page 1 of 3

Reconfigurable Machine

In order to maintain advantages of partitioning input variables into groups of two inputs each, when implementing system functions in array logic networks employing partitioned input decoding, it is desirable to preserve the redundancy and reconfigurability capabilities inherent in array logic structures. It is also desirable to maintain a flexibility of interconnection among communicating array logic structures, so that interrelated engineering changes in a network of array structures may be accommodated, without resorting to the difficult and expensive expedient of inserting "yellow" wires.

Described is a "flexible" personalized decoder in a cross-point array structure (see Fig. 1) which, in conjunction with writeable AND-array and OR-array structures of conventional array logic configurations, provides selective partitioned decode capability. With circuit redundancy per array this enables related engineering changes to be propagated throughout a multiarray network without wiring changes.

Referring to Fig. 1, it is noted that each input drives a pair of vertical lines, with an inverter interposed in one line of each pair. Each pair of lines represents a one input decodes for the respective input function. Each horizontal line represents a wired-OR logical decoding operation on the combined outputs driving the line. The "1's" and "0"s at cross-points denote information stored in, not shown, cross-point latching elements which are conditionable through a, not shown, conditioning network. The inverter on the output or each horizontal line converts the logical OR into a NOR (or NAND) function.

For example, the output A.C will be explained. At the intersection of the two lines driven by input A, a 0 is stored at the left intersection, and a 1 is stored at the right (A) intersection. If A is present, then the left vertical line is driven, but the stored 0 prevents coupling to the horizontal line associated with A.C. However, if A is present, the right vertical line is driven, and because 1 is stored at the first row intersection, an output signal appears on the horizontal line associated with A.C. Because of stored 0's, B, B, C, D and D will not drive the first horizontal line; and because of a stored 1, C will drive the line. Consequently, a...