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Design Automation for Vertical Adjacency and Horizontal Direct Optimization

IP.com Disclosure Number: IPCOM000081019D
Original Publication Date: 1974-Mar-01
Included in the Prior Art Database: 2005-Feb-27
Document File: 4 page(s) / 36K

Publishing Venue

IBM

Related People

Atkins, JD: AUTHOR

Abstract

Channel space utilization is critical in design automation systems. This is the physical space in which the wires are placed. In general, more channel space is always desirable. Although repartitioning cannot insert additional channels in the middle of a logic card, the repartitioning function can open up channel space through the physical alteration of the net list. This is accomplished by modifying networks which include multiple pins on the same vendor transistor logic (VTL) module. If a set of pins representing a network contains two pins which are vertically adjacent on one VTL module, these two pins can be wired without using any channel space on the logic card. Such a connection is also guaranteed wirable.

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Design Automation for Vertical Adjacency and Horizontal Direct Optimization

Channel space utilization is critical in design automation systems. This is the physical space in which the wires are placed. In general, more channel space is always desirable. Although repartitioning cannot insert additional channels in the middle of a logic card, the repartitioning function can open up channel space through the physical alteration of the net list. This is accomplished by modifying networks which include multiple pins on the same vendor transistor logic (VTL) module. If a set of pins representing a network contains two pins which are vertically adjacent on one VTL module, these two pins can be wired without using any channel space on the logic card. Such a connection is also guaranteed wirable. Repartitioning creates these connections by swapping portions within a VTL module and by exchanging the input pins within a portion.

The creation of these vertically adjacent connections also eliminates conditions that may seriously impair the wirability of a VTL logic card. If two nonadjacent pins on a VTL module are involved in the same net, the connection between these two pins is often difficult to wire. Although the distance between the two pins is relatively small, it is necessary to use a via to change the direction of the wire, if the two pins do not lie on a straight line parallel or perpendicular to the edge of the card. There are two columns of vias between the two pin columns on the module, but not all of those vias are available for wiring the connection. Some are used as voltage sources for the VTL module. Thus, a via may not be available within the rectangular boundary of the connection to change the direction of the wire.

If the nonadjacent connection can be wired, little channel space may actually be used. But the channel space required for the connection may prevent the routing of a longer connection that spans the area where the VTL module resides. The vertically adjacent connections that result from the repartitioning phase improve the wirability of a VTL logic card in two ways. Additional connections on the logic card are guaranteed wirable, and the channel space and vias made available by creating the vertically adjacent connections, enhance the possibility of wiring other connections on the logic card.

Via requirements may be reduced by establishing direct connections within a net, that is, connections between two pins which lie on a straight line parallel or perpendicular to the bottom edge of the card. Such a connection may be wired without using vias. If a nondirect connection can be altered to produce a direct horizontal connection, an additional benefit is realized in terms of channel space utilization. Consider the area of a square on a VTL logic card containing two adjacent 16-pin VTL modules. The vertical density of pins in this unit of area is twice the horizontal pin density. This pin density ratio is approximately...