Browse Prior Art Database

Dynamic Patch for Read Only Storage Program

IP.com Disclosure Number: IPCOM000081022D
Original Publication Date: 1974-Mar-01
Included in the Prior Art Database: 2005-Feb-27
Document File: 2 page(s) / 24K

Publishing Venue

IBM

Related People

Garriss, DS: AUTHOR [+4]

Abstract

Current technology in microprocessing systems uses read-only storage (ROS) hardware as the storage for the microcode programs used in the machine. The ROS modules cannot be changed in the field, and changes in manufacturing require many weeks due to process and cycle time. When problems or requirements arise which require the altering of ROS, it is highly desirable to first evaluate the change by testing the altered ROS code on the machine before the changes are incorporated into a hardware ROS module.

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Dynamic Patch for Read Only Storage Program

Current technology in microprocessing systems uses read-only storage (ROS) hardware as the storage for the microcode programs used in the machine. The ROS modules cannot be changed in the field, and changes in manufacturing require many weeks due to process and cycle time. When problems or requirements arise which require the altering of ROS, it is highly desirable to first evaluate the change by testing the altered ROS code on the machine before the changes are incorporated into a hardware ROS module.

A solution to this problem lies in the Dynamic ROS Patch. A small adapter is provided in the machine which consists of an address register 1, a memory address bus 2 from the processor, and a comparator 3 which drives an interrupt unit 4.

In using the dynamic ROS patch adapter, the machine is programmed to load the address register 1 from a settable random-access memory 5 with the last valid address of the program section being executed. The address in register 1 is continuously compared in comparator 3 for equality with the instruction address on bus 2. When an equality is found, the equal output from comparator 3 is passed to an instruction interrupt section of the microprocessor. Upon reception of the interrupt signal, the processor will branch to a designated instruction address in the random-access memory 5 for its next program instruction. Normally, this will be the first instruction of the storage section containing...