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Asymmetrical Clock

IP.com Disclosure Number: IPCOM000081028D
Original Publication Date: 1974-Mar-01
Included in the Prior Art Database: 2005-Feb-27
Document File: 2 page(s) / 45K

Publishing Venue

IBM

Related People

Duggan, CJ: AUTHOR

Abstract

An oscillating waveform is generated which has a period that is an odd integer multiple of one-half the oscillator period. This arrangement enables a computer system to have a single-crystal oscillator and yet provide timing signals for I/O devices which, in some instances, require an odd integer multiple of one-half the crystal oscillator period.

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Asymmetrical Clock

An oscillating waveform is generated which has a period that is an odd integer multiple of one-half the oscillator period. This arrangement enables a computer system to have a single-crystal oscillator and yet provide timing signals for I/O devices which, in some instances, require an odd integer multiple of one- half the crystal oscillator period.

In Fig. 1 oscillator 10 has a period of (N) nanoseconds and a period of Y(N) over 2 is desired, where Y is an odd integer. If N=100 nanoseconds, a period of 450 nanoseconds is generated when Y=9; i.e., 450 = 9(100) over 2. The output of oscillator 10 is applied to exclusive OR circuit 15. The output of exclusive OR circuit 15 provides the clocking pulse to J-K flip-flops 20, 25, 30 and 35. The J input of flip-flop 20 is tied to ground. The J inputs of flip-flops 25 and 35 are controlled by AND circuit 22 and the J input of flip-flop 30 is controlled by AND circuit 26. AND circuits 36, 21, 27 and 31 control the K inputs of flip-flops 20, 25, 30 and 35, respectively.

The clock output is taken from OR circuit 40 which passes the outputs of AND circuits 37, 38 or 39. AND circuit 37 combines the reset outputs of flip-flops 25 and 30, respectively. The set output and reset output of flip-flops 25 and 30, respectively, are applied to AND circuit 38. AND circuit 39 receives the reset outputs of flip-flops 20 and 25, respectively.

The clock pulse passed by exclusive OR circuit 15 is logically dependent upon t...