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Clock and Power Distribution System for Josephson Tunneling Logic Networks

IP.com Disclosure Number: IPCOM000081045D
Original Publication Date: 1974-Mar-01
Included in the Prior Art Database: 2005-Feb-27
Document File: 2 page(s) / 38K

Publishing Venue

IBM

Related People

Anacker, W: AUTHOR

Abstract

A combined clock and power distribution system for Josephson tunneling logic network is proposed, as shown in principle form in Fig. 1. A, B, C and D denote logic circuits (schematically only, without concern of actual logic functions performed). The logic circuits A, B, C and D constitute a combinatorial network which is to be activated during specific clock cycles by way of the application of a clock select pulse.

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Clock and Power Distribution System for Josephson Tunneling Logic Networks

A combined clock and power distribution system for Josephson tunneling logic network is proposed, as shown in principle form in Fig. 1. A, B, C and D denote logic circuits (schematically only, without concern of actual logic functions performed). The logic circuits A, B, C and D constitute a combinatorial network which is to be activated during specific clock cycles by way of the application of a clock select pulse.

The requirements for operation of the logic circuits A, B, C and D are: (a) that during a selected clock cycle a gate current is flowing through them, which can be directed under the influence of control currents in the logic circuits to flow in part through the resistors R(1); and (b) that the gate current is reduced after a selected clock cycle, to cause the gates in the logic circuits which may have been switched to V = V(g) to switch back to the V = 0 state.

The operating conditions are estahlished in the following way: (1) Since the resistor R(2) prevents currents to flow through the right long branch in the quiescent state, the DC current I(dc) flows through the left long branch in Fig. 1 and through the series of "clock select" gates which are in the V = 0 state: (2) Upon application of the clock select pulse sequence shown in Fig.2, the clock select gates are switched and develop a voltage (n x V(g)) in the left branch and, in consequence, cause a current (n x V(g)/R(2)) to be directed into the right branch. Design is such that the...