Browse Prior Art Database

2 Cryotron, 2 Line Nondestructive Read or Destructive Read Memory

IP.com Disclosure Number: IPCOM000081065D
Original Publication Date: 1974-Mar-01
Included in the Prior Art Database: 2005-Feb-27
Document File: 4 page(s) / 39K

Publishing Venue

IBM

Related People

Schlig, ES: AUTHOR

Abstract

This memory array incorporates two Josephson tunneling devices per cell and two connecting array lines, which can operate in either of two modes depending on the relative characteristic impedance of the bit-sense line. The two modes are:

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2 Cryotron, 2 Line Nondestructive Read or Destructive Read Memory

This memory array incorporates two Josephson tunneling devices per cell and two connecting array lines, which can operate in either of two modes depending on the relative characteristic impedance of the bit-sense line. The two modes are:

1. non destructive read (NDR) with a relatively low amplitude sense signal, or

2. destructive read (DR) with a relatively large sense signal.

Fig. 1 is a schematic diagram of 2x2 array of two Josephson tunneling devices, two-line memory cells 1. All paths are superconductive, and may be in proximity to and insulated from a superconductive ground plane.

Control lines 2 for sense gates "A" and cell gates "B" are in series with the word lines WL1, WL2. Gate A has an additional control LA, which is in series with the shunt path L of cell 1. Gate A is controlled by the superposition of the two control currents in line 2 and LA. Gate current is applied to cells 1 via bit sense lines BL1, BL2.

For the modes of operation detailed below, gate B is an asymmetrical in-line gate with a length several times larger than Lambda j or an asymmetrical multiple bridge interferometer gate, while gate A is a symmetrical gate such as a crossed- control gate or a symmetrical interferometer gate. The relationships among the thresholds of the two gates which will become apparent from the discussion below, are obtained in ways known in the art by means of the geometry of the gates and controls.

Fig. 2 is representative of the gain characteristics of the symmetrical and asymmetrical devices mentioned above, with gate A being the former and gate B being the latter.

In the following, persistent current in loop L is defined as the "one" state. WRITE OPERATION:

All cells 1 of the selected word are unconditionally reset to "zero" state by means of a negative word pulse on WL1, WL2 before writing. No bit current is applied during reset. The amplitude of the reset word pulse is such that each gate B is switched if the cell is in the "one" state, causing the circulating current to be reduced to a very small value. If cell 1 is already in the "zero" state, it remains in that state.

Writing is performed by applying a positive word pulse to the selected word line WL1, for example. For those cells into which a "zero" is to be written, the associated bit lines are quiescent during the word pulse application.

For those cells into which a "one" is to be written, the associated bit lines are pulsed positively during the word pulse application. When writing "zero" neither gate A or gate B is switched and circulating current in loop L remains at a low

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level. When writing "one," if, for example, the bit pulse is initiated first, bit current in cell 1 divides between gate B and loop L. Because the inductance of the former is much lower than that of the latter, most of the bit current flows through gate B. Upon application of the word pulse which overlaps the bit pu...