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Browse Prior Art Database

Variable Delay Pulse Circuits

IP.com Disclosure Number: IPCOM000081084D
Original Publication Date: 1974-Apr-01
Included in the Prior Art Database: 2005-Feb-27
Document File: 3 page(s) / 50K

Publishing Venue

IBM

Related People

Marino, PT: AUTHOR

Abstract

Two pulse delay circuits, one for receiving a single-ended pulse signal and a second for receiving a differential pulse input signal, are inherently stable to enable precise pulse delays in the nanosecond range. The range of delay variation is an order of magnitude. The circuits are both integratable. Clamping capacitor circuits in the delay determining portion of the pulse delay circuits enhances operation of both embodiments.

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Variable Delay Pulse Circuits

Two pulse delay circuits, one for receiving a single-ended pulse signal and a second for receiving a differential pulse input signal, are inherently stable to enable precise pulse delays in the nanosecond range. The range of delay variation is an order of magnitude. The circuits are both integratable. Clamping capacitor circuits in the delay determining portion of the pulse delay circuits enhances operation of both embodiments.

In the single-ended input signal embodiment shown in Fig. 1, when the single-ended signal goes positive, transistors T1 and T6 are made current conductive. The current flow through T6 via R3 makes the base electrode of transistor T5 relatively negative. T5 then becomes current nonconductive, which allows the voltage VA at the collector of T1 to fall at a rate determined by the values of resistor R1, capacitance C1, and the amplitude of current flowing through T8. At the same time, in accordance with the differential action between transistors T1 and T2, the voltage VB on transistor T2 rises to positive voltage VS at a rate determined by R2, C2, and the clamp reference potential of T3. When the voltage VA = VB, the differential output signal VB - VA becomes . positive; hence. determines the pulse delay from the input at the base electrode of T6 to the differential output. For purposes of brevity, output squaring circuits are not shown.

The pulse delay is determined by the amplitude of current flowing through transistors T1 and T2, as controlled by transistor T8. As the current through T8 increases, the delay time from the input terminal to the output terminals is decreased. For maximum current through T8, there is a short delay; and for minimum current, there is a long delay. By making the control voltage on TR continuously variable, any intermediate delay can be achieved.

The above-described circuit responds only to positive-going transitions. Hence, the circuit must recover rapidly, as shown at the recovery time on the negative transition of the single-ended input signal. When the single-ended input signal goes negative, transistors T6 and T1 become current nonconductive. This forces T2 to become current conductive for discharging C2 and lowering VB to a reference potential controlled by clamp transistor T3. VB recovers rapidly to the clamp level if R2 > R1. This minimizes the effects of the current amplitude in T8 on the recovery time. Simultaneously, voltage VA rises quickly to a value VP minus the base-emitter drop across transistor T5. R4 is used as a damping resistor to eliminate overshoot when VA rises to its up level. Base-emitter voltage tracking on T3 and T4 give a stable voltage swing on VB, en...