Browse Prior Art Database

Stepping Motor Control System

IP.com Disclosure Number: IPCOM000081114D
Original Publication Date: 1974-Apr-01
Included in the Prior Art Database: 2005-Feb-27
Document File: 3 page(s) / 53K

Publishing Venue

IBM

Related People

Abraham, DG: AUTHOR

Abstract

This stepping motor control system uses a read-only storage to derive the appropriate control pulses for operating the stepper motor.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 54% of the total text.

Page 1 of 3

Stepping Motor Control System

This stepping motor control system uses a read-only storage to derive the appropriate control pulses for operating the stepper motor.

It is assumed that a host computer or other control determines the effective number of steps which the motor is required to advance, as control system.

The actual generation of the motor phase driver input signals from a stream of advance pulses is well known in the art and will not be discussed. It is assumed, however, that a bidirectional 2-bit Johnson or Grey code counter is used. Pulse injection techniques are used to control the field configuration of the motor, therefore, the input advance pulse stream will contain "extra" pulses in the one and two step modes.

The basic philosophy involved in this system is:
1) Utilize an oscillator and down counter as a stable drift-free

single-shot to generate the motor advance pulses.
2) Utilize a read-only store (ROS) to store the length of each

single-shot pulse required for each different length move.
3) Utilize a portion of the ROS to store the address of the

first instruction in the same address corresponding to the

length of the move (e.g., the address of the first

instruction for a five-step move is stored at address five).
4) Preload a counter with the address of the first instruction

and feed this address back onto the ROS address lines, to

call up the length of the first advance pulse.
5) This length or time interval data--in this case one byte

indicating an 8-bit binary number equal to the desired time

interval divided by the oscillator period--is loaded into

the time interval counter (TIC) mentioned in (1.) above.
6) Each instruction is executed serially until the move has

been completed.

For example, an oscillator with an 8 usec period and an 8-bit data/ down counter configuration can be assumed. This configuration allows pulses from 8 usec to 2.04 msec to be generated in 8 usec steps. The ROS in this example actually consists of 3 separate ROS's.

Referring to Fig. 1, the length of the move in steps is put onto the 4-bit input bus 3 in binary form. After the data is solid on the bus, the move command line 5 is brought up by the host system. The data is then latched up into the 4-bit move length latch 7 and the system busy latch 9 is set. The data may now drop from the input lines. The output of the latches is presented to the memory element decode (MED) 11, 1 or 2-step decode and preload for the move length counter 13, and input A of the 5-bit data selector 15. Since the move length counter (MLC) 17 has not been loaded yet, the output of the 0 decode 19 is true. This sets or rather holds set the MED inhibit latch 21. This latch forces:
1. The 5-bit data selector 15 to place the contents of the A

1

Page 2 of 3

input (the length of the move) on the read-only store (ROS)

address bus 23.
2. Enables ROS-I via OR circuit 25 and inhibits the MED decode

circuits 11.

ROS-I is arranged such that the...