Browse Prior Art Database

Using a Random-Access Memory as a Shift Register

IP.com Disclosure Number: IPCOM000081124D
Original Publication Date: 1974-Apr-01
Included in the Prior Art Database: 2005-Feb-27
Document File: 2 page(s) / 35K

Publishing Venue

IBM

Related People

Ho, AP: AUTHOR [+2]

Abstract

A serious drawback of a large-scale shift register is its reliability. If one of the stages malfunctions, e.g., a stuck bit at either 1 or 0, the output of the register is incorrect. Large-scale random-access memories, on the other hand, are becoming very economical and reliable. In addition, they are commonly associated with error correction systems to further assure reliability. The present system uses a random-access memory as a shift register.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 100% of the total text.

Page 1 of 2

Using a Random-Access Memory as a Shift Register

A serious drawback of a large-scale shift register is its reliability. If one of the stages malfunctions, e.g., a stuck bit at either 1 or 0, the output of the register is incorrect. Large-scale random-access memories, on the other hand, are becoming very economical and reliable. In addition, they are commonly associated with error correction systems to further assure reliability. The present system uses a random-access memory as a shift register.

Referring to Fig. 1, random-access memory 2 is sequentially addressed by ring counter 4. This serves to shift the particular word location in the random- access memory 2 sequentially once per cycle. The data to be shifted is transmitted serially to location 0 of input register 5. The word in the random- access memory 2 is transmitted to output register 6. The output signals of output register 6 are transmitted to the input register 5 with a skew of one bit. During the next cycle, the next data bit is received at location 0 of input register 5 and this new word is written into random-access memory 2 to continue the operation.

An operational flow chart for the process is illustrated in Fig. 2. An error correction system may also be connected between the input and output registers to improve reliability.

1

Page 2 of 2

2

[This page contains 2 pictures or other non-text objects]