Browse Prior Art Database

Preemptive Loader for a Central Processing Unit

IP.com Disclosure Number: IPCOM000081128D
Original Publication Date: 1974-Apr-01
Included in the Prior Art Database: 2005-Feb-27
Document File: 2 page(s) / 58K

Publishing Venue

IBM

Related People

Giaccone, LF: AUTHOR [+2]

Abstract

This is a means to cause arbitrary, externally generated, interruptions of a central processing unit (CPU) code for testing purposes' The system in Fig. 1 solves the problems caused by attaching nontest or nontested devices to a CPU test bed. The flow diagram in Fig. 2 illustrates the operation of the preempt device, termed an Interrupt Generator.

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Preemptive Loader for a Central Processing Unit

This is a means to cause arbitrary, externally generated, interruptions of a central processing unit (CPU) code for testing purposes' The system in Fig. 1 solves the problems caused by attaching nontest or nontested devices to a CPU test bed. The flow diagram in Fig. 2 illustrates the operation of the preempt device, termed an Interrupt Generator.

The interrupt generator places an artificial, but measurable load on the CPU equivalent to an I/O device and its associated control code on any unused interrupt level by producing interrupts on the I/O interface of variable duration and frequency.

For a CPU which may be interrupted by an input-output I/O device the generator is wired to one of the I/O bus lines. The generator monitors the I/O line to determine if the interrupt (IRPT) is permissible. If it is, the IRPT line is raised, thereby causing the CPU to switch levels. The I/O line is constantly monitored to insure that the generator resets if it is raised.

In operation, the generator transmits an IRPT signal to the CPU. The time data (TD) signals are counted in counter 1 until equal in number to the setting on switch 1. At that time, the IRPT signal to the CPU is removed via the latch. The TD signals are then counted in counter 2 until equal in number to the setting on switch 2. At that time the IRPT signal is again transmitted to the CPU.

The interrupt generator does not interfere with any I/O operation in progress...