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Small Signal Receiver Circuit For Complementary Metal-Oxide Semiconductor Circuits

IP.com Disclosure Number: IPCOM000081130D
Original Publication Date: 1974-Apr-01
Included in the Prior Art Database: 2005-Feb-27
Document File: 2 page(s) / 36K

Publishing Venue

IBM

Related People

Daoust, PJ: AUTHOR [+2]

Abstract

In general, complementary metal-oxide semiconductor (CMOS) circuits are designed to operate with zero standby current. This produces voltage swings equal to the power supply. In cases where the input to CMOS logic is derived from a different technology the input swing is not sufficient to fully turn off complementary devices in series, producing power dissipation in one or the other input state. The circuit shown in the drawing overcomes this discrepancy and eliminates all current paths for steady-state conditions. In the drawing, all P devices substrates are tied to +V and all N devices substrates are tied to GND.

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Small Signal Receiver Circuit For Complementary Metal-Oxide Semiconductor Circuits

In general, complementary metal-oxide semiconductor (CMOS) circuits are designed to operate with zero standby current. This produces voltage swings equal to the power supply. In cases where the input to CMOS logic is derived from a different technology the input swing is not sufficient to fully turn off complementary devices in series, producing power dissipation in one or the other input state. The circuit shown in the drawing overcomes this discrepancy and eliminates all current paths for steady-state conditions. In the drawing, all P devices substrates are tied to +V and all N devices substrates are tied to GND.

To understand the operation, the input is first assumed to be at 0. For this condition, N2 is off, P2 is on, node A is at +V forcing N3 to be on, P3 to be off and node B to be at ground, which forces P1 to be off allowing N1 to keep node C down and therefore P2 on.

P4 and N4 form a normal CMOS inverter dissipating no DS power, and, therefore will be left out of the description.

Note that with ground input, one device in each series path from +V to ground is off.

As the input is raised up, N2 turns on, node A starts to drop. Node B rises, turning P1 on and forcing P2 to turn off. This allows A to drop down to ground, turning N3 off. As the input continues to rise, the source to substrate bias of N1 is increased to such a degree that N1 turns off. So that again in steady s...