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AC Test Procedure for Redundant Functional Islands

IP.com Disclosure Number: IPCOM000081147D
Original Publication Date: 1974-Apr-01
Included in the Prior Art Database: 2005-Feb-27
Document File: 2 page(s) / 28K

Publishing Venue

IBM

Related People

McMahon, MT: AUTHOR

Abstract

Where a large-scale integrated (LSI) logic design employs redundancy in the form of functional islands, this arrangement employs the redundancy to provide a built-in AC testing capability.

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AC Test Procedure for Redundant Functional Islands

Where a large-scale integrated (LSI) logic design employs redundancy in the form of functional islands, this arrangement employs the redundancy to provide a built-in AC testing capability.

Each equivalent output of the two identical functional islands, 1 and 1', that make up a functional unit 2, will be connected to an exclusive OR 3. Each exclusive OR will drive a gated latch 4 through an inverter 5 in such a manner that the latch output will be set to an error code, if the two functional island outputs are at a different logical value for greater than a predetermined time period.

The inverter 5 is used as the time reference between the two outputs that feed the exclusive OR 3. The longer the delay of the inverter 5, the larger the time difference allowed before the gated latch 4 will latch an error code (logical 0 level). The inverter 5 may be a standard unit of delay, representing a typical circuit delay on the chip, or it may be a circuit where the delay can be adjusted by varying the loading on an I/O driven by the inverter. When the output of the exclusive OR 3 is at a logical 1 level for a period greater than the switching time of the inverter, the gated latch 4 will remain at a logical 0 state.

The testing procedure consists of applying identical functional patterns to the two functional islands 1, 1' making up a functional unit 2. The latch outputs are interrogated after each input pattern is applied to...