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Complementary Metal Oxide Semiconductor J/K Flip Flop and Shift Cell

IP.com Disclosure Number: IPCOM000081159D
Original Publication Date: 1974-Apr-01
Included in the Prior Art Database: 2005-Feb-27
Document File: 2 page(s) / 49K

Publishing Venue

IBM

Related People

Pomeranz, JN: AUTHOR

Abstract

The circuit shown in Fig. 1 is a complementary metal-oxide semiconductor (CMOS) J-K flip-flop that is suitable for integration into large and fully testable large-scale integrated (LSI) chips. The circuit not only will operate as a normal J-K cell, but has shift capability to input test patterns into a string of such cells and to shift these from cell-to-cell. After testing the chip in the normal mode, the resulting data in the cells can be shifted out.

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Complementary Metal Oxide Semiconductor J/K Flip Flop and Shift Cell

The circuit shown in Fig. 1 is a complementary metal-oxide semiconductor (CMOS) J-K flip-flop that is suitable for integration into large and fully testable large-scale integrated (LSI) chips. The circuit not only will operate as a normal J- K cell, but has shift capability to input test patterns into a string of such cells and to shift these from cell-to-cell. After testing the chip in the normal mode, the resulting data in the cells can be shifted out.

The circuit as shown in Fig. 1 is composed of 2 latches, a primary and secondary latch. Data to the primary latch can be entered two ways, i.e., either by inputs J, K in combination with clock C, or by inputs S Phi, S Phi and clock A. Data is shifted into the secondary latch by the shift clock B.

Fig. 2 shows the patterns for normal and shift operations. For normal operation, Clocks B and C are used and the cell exhibits the four J-K flip-flop functions of set 1, met 0, toggle, and hold. When used as a shift register, clocks A and B are used. It should be noted that the next cell in the shift register, not shown, receives S1 and S1 as inputs.

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